Floorplanning for Versal Devices - 2025.1 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
Document ID
UG909
Release Date
2025-05-29
Version
2025.1 English
As part of improvements to the Versal architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type, and are referred to as a Programmable Unit (PU). Many site types have improved PU requirement making granularity of reconfigurable Pblocks significantly improved compared to previous architecture.
Tip: Although the fundamental building blocks are shown in the following images, in real design scenarios these building blocks are part of a larger collection of resources, creating a comprehensive floorplan for each dynamic region.

You can use get_dfx_footprint -pu -of_objects [get_tiles <tile_name>] to get the PU of any tile in a Versal device. For information, enter get_dfx_footprint -help. The PUs are not design dependent. You can load any device with link_design -part <device_name> or create an I/O planning project and use the get_dfx_footprint command with the -pu switch to get the PU of any tile. Following are the details provided for each site type.

Programmable Logic (PL) NoC NMU and NSU

The PU is the corresponding NOC_NMU or NOC_NSU tile and includes 38 INTF and the shared INT tiles.

Figure 1. PL NoC NMU and NSU

CLE

Two adjacent CLE tiles share a routing resource (interconnect tile). The PU is the two CLE tiles (four SLICE sites) with shared interconnect.

Figure 2. CLE PU

Block RAM

The PU is the corresponding block RAM tile. One block RAM tile includes two RAMB18s and one RAMB36. Adjacent INTF and INT tiles, including IRI_QUAD_EVEN and IRI_QUAD_ODD, are automatically pulled into the routing footprint if it is not covered by the Pblock. Unlike previous architectures, adjacent CLE sites are not part of the block RAM PU.

Figure 3. Block RAM PU: RAMB18s and RAMB36 of One Block RAM Tile

URAM

The URAM PU includes 1 URAM288, 1 URAM_CAS_DLY, IRI_QUAD_EVEN, and IRI_QUAD_ODD. The adjacent INTF and INT tiles are automatically pulled into the routing footprint if it is not covered by the Pblock.

Figure 4. URAM PU: URAM Tile

DSP

The PU is the corresponding DSP tile. One DSP tile includes two DSP sites: DSP58_PRIMARY, DSP58_CPLX and IRI_QUAD_EVEN, IRI_QUAD_ODD.

Figure 5. DSP PU: DSP Tile

IRI_QUAD (ODD/EVEN)

The PU is the corresponding INTF_ROCF_TL_TILE. One tile includes four IRI Quads. The INTF at the center of the IRI quads is automatically pulled into the routing footprint. Although IRI_QUADs are user range-able, the adjacent IRI_QUADs of the RP Pblock are automatically pulled into the routing footprint, because the expanded routing footprint is always a two INT tile expansion.

Figure 6. IMUX Register Interface Quad: PU is INT_ROCF_TL Tile

PCIe

The PU is the IRI_QUAD_EVEN, IRI_QUAD_ODD, and PCIE50. The adjacent INTF tiles are automatically included in the routing footprint of the reconfigurable Pblock.

Figure 7. PCIe PU is PCIe Tile

GTY_QUAD

The PU is the corresponding GTY_QUAD_SINGLE tile. Sites included in the tile are GTY_QUAD, GTY_REFCLK, and IRI_QUAD. The adjacent INTF_GT tiles are automatically pulled into the routing footprint of the reconfigurable Pblock.

Figure 8. GTY_QUAD PU is GTY_QUAD Tile

DDRMC and DDRMC_RUI

The PUs are the corresponding DDRMC_DMC_CORE and DDRMC_RIU_CORE tiles respectively. For information, run the following command:
get_dfx_footprint -pu -of_objects [get_tiles -of_objects [get_sites DDRMC_RIU_X2Y0]]
DDRMC_DMC_CORE_X65Y0 DDRMC_RIU_CORE_X55Y0
Figure 9. DDRMC PU

MMCM

The PU is a corresponding CMT_MMCM tile.

Figure 10. MMCM PU is CMT_MMCM Tile

XPLL

The PU is the corresponding CMT_XPLL tile.

Figure 11. XPLL PU is CMT_XPLL Tile

DPLL

The PU is the corresponding CMT_DPLL tile.

Figure 12. DPLL PU is CMT_DPLL Tile

MRMAC

The PU includes the MRMAC_BOT_TILE and the IRI_QUAD_EVEN and IRI_QUAD_ODD sites. The adjacent INT and INTF tiles are automatically included in the routing footprint of the reconfigurable Pblock.

Figure 13. MRMAC PU

BUFG_FABRIC, BUFG_PS and GCLK_DELAY

These three site types are included in same CLK_VNOC tile. BUFG_PS is present only in the VNOC column adjacent to CIPS. Other VNOC tiles include only BUFG_FABRIC and GCLK_DELAY. The PU requirement is the CLK_VNOC tile and IRI_QUADS.

Figure 14. BUFG_FABRIC, BUFG_PS, and GCLK_DELAY Shares Same Tile As PU

XPHY, XPIO, and IOB

An I/O bank in Versal devices cannot be shared by static and reconfigurable partitions. All XPIO_NIBBLE tiles of one I/O bank must be used by one partition only.

Figure 15. XPHY, XPIO and IO PU

BUFG_GT, BUFG_GT_SYNC, and GCLK_DELAY

The CLK_GT tile and the IRI_QUAD sites are included in the PU.

Figure 16. BUFG_GT, BUFG_GT_SYNC Share Same PU: CLK_GT Tile

XPIPE_QUAD

The XPIPE_QUAD tile is the PU,which includes IRI_QUAD_EVEN, IRI_QUAD_ODD,GTY_QUAD, GTY_REF_CLK, and XPIPE_QUAD.

Figure 17. XPIPE_QUAD PU

BUFGCE, BUFGCTRL, and BUFGCE_DIV

For the BUFGCE elements in HSR, the PU is the CLK_REBUF_BUFGS_HSR_CORE tile.

Figure 18. Clocking Buffers in HSR Has CLK_REBUF_BUFG_HSR_CORE Tile As PU

BUFGCE_HDIO, HDIO_BIAS, HDIO_LOGIC, and IOB

For these sites in HDIO, the PU is the HDIO_TILE tile and the IRI_QUADs.

Figure 19. Clock Buffers and IOB in HDIO Bank Share Same PU: HDIO_TILE

High-speed Channelized Cryptography Engines (HSC)

The PU is the corresponding HSC_TILE tile and IRI_QUADs.

Figure 20. HSC PU: HSC Tile

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