As part of improvements to the Versal
architecture, the smallest unit that can be reconfigured is much smaller than in
previous architectures. The minimum required resources for reconfiguration varies based
on the resource type, and are referred to as a Programmable Unit (PU). Many site types
have improved PU requirement making granularity of reconfigurable Pblocks significantly
improved compared to previous architecture.
Tip: Although the fundamental building blocks are shown in the following images, in real
design scenarios these building blocks will be part of a larger collection of
resources, creating a comprehensive floorplan for each dynamic region.
You can use get_dfx_footprint -pu -of_objects
[get_tiles <tile_name>] to get the PU of any tile in a Versal device. For information, enter get_dfx_footprint -help. The PUs are not design dependent. You can load any device with
link_design -part <device_name> or create an
I/O planning project and use the get_dfx_footprint
command with the -pu switch to get the PU of any
tile.
Following are the details provided for each site type.
- Programmable Logic (PL) NoC NMU and NSU
- The PU is the corresponding NOC_NMU or NOC_NSU tile and includes 38 INTF
and the shared INT tiles.Figure 1. PL NoC NMU and NSU
- CLE
- Two adjacent CLE tiles share a routing resource (interconnect tile). The PU
is the two CLE tiles (four SLICE sites) with shared interconnect.Figure 2. CLE PU
- Block RAM
- The PU is the corresponding block RAM tile. One block RAM tile includes two
RAMB18s and one RAMB36. Adjacent INTF and INT tiles, including IRI_QUAD_EVEN and
IRI_QUAD_ODD, are automatically pulled into the routing footprint if it is not
covered by the Pblock. Unlike previous architectures, adjacent CLE sites are not
part of the block RAM PU.Figure 3. Block RAM PU: RAMB18s and RAMB36 of One Block RAM Tile
- URAM
- The URAM PU includes 1 URAM288, 1 URAM_CAS_DLY, IRI_QUAD_EVEN, and
IRI_QUAD_ODD. The adjacent INTF and INT tiles are automatically pulled into the
routing footprint if it is not covered by the Pblock.Figure 4. URAM PU: URAM Tile
- DSP
- The PU is the corresponding DSP tile. One DSP tile includes two DSP sites:
DSP58_PRIMARY, DSP58_CPLX and IRI_QUAD_EVEN, IRI_QUAD_ODD.Figure 5. DSP PU: DSP Tile
- IRI_QUAD (ODD/EVEN)
- The PU is the corresponding INTF_ROCF_TL_TILE. One tile includes four IRI
Quads. The INTF at the center of the IRI quads is automatically pulled into the
routing footprint. Although IRI_QUADs are user range-able, the adjacent
IRI_QUADs of the RP Pblock are automatically pulled into the routing footprint,
because the expanded routing footprint is always a two INT tile expansion.Figure 6. IMUX Register Interface Quad: PU is INT_ROCF_TL Tile