Hardened DDR Memory Controllers - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

Hardened DDR memory controllers (DDRMCs) in AMD Versalâ„¢ is implemented using NoC IP Wizard. User can choose to keep DDRMCs in either static region or reconfigurable partition. There are certain recommendation while using DDRMCs in a DFX design. They are:

  • It is not recommended to share a DDRMC between static region and reconfigurable partition or between multiple reconfigurable partitions.
  • If a DDRMC port is shared between static and reconfigurable module (RM), traffic class and bandwidth requirements on static path can impact the traffic class and bandwidth of RM. User should consider overall static and RM usage requirement of NoC and allocate just enough bandwidth and QoS for static so that reconfigurable module gets more flexibility to meet its requirement. A NoC channel supports only two traffic classes. Hence if two traffic classes are already consumed by static region, no new traffic class can be used by the reconfigurable module. Please refer to Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) to learn more about Traffic Class, Virtual Channel and QoS of NoC.
  • If certain use cases demand sharing of DDRMC between static and reconfigurable partition, NoC INI based connection can be used at static-RM interface for logic to communicate to DDRMC in other partition.
  • When DDRMC is instantiated in the reconfigurable partition, include the necessary resources in the corresponding reconfigurable Pblock.

    Given below is a block diagram representation of Hard DDRMC usage in a DFX design. Three different usage of DDRMCs are shown below. They are:

    • Static Logic accessing Static DDRMC. This is shown in the magenta color where CIPS in static region is accessing DDRMC in static region using AXI NOC Interface IP.
    • AXI Traffic Generator in reconfigurable partition writing data to DDRMC inside the reconfigurable partition itself. This path is highlighted in brown color.
    • AXI Traffic Generator in Reconfigurable partition writing data to DDRMC in static region using NoC Inter-NoC-Interconnect (INI). This path is shown in dark blue color.
      Figure 1. Hardened DDR Memory Controllers