Creating Pblocks for UltraScale and UltraScale+ Devices - 2024.2 English - UG909

In the UltraScale architecture, the smallest unit that can be reconfigured is smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type and are referred to as a programmable unit (PU). Because adjacent sites share a routing resource (or interconnect tile) in UltraScale devices, a PU is defined in terms of pairs.

Following are examples of some of the minimum PU that can be reconfigured based on the site types:

CLB PU

Includes two adjacent CLBs and the shared interconnect.

Figure 1. CLB PU

Block RAM PU

Includes one RAMBFIFO36, two RAMB18, five adjacent CLBs, and the shared interconnect. The PU is the corresponding block RAM tile. One block RAM tile includes RAMBFIFO18, FIFO18_0, RAMB180, RAMB181, RAMBFIFO36, FIFO36, and RAMB36. Adjacent CLE sites are part of the block RAM PU.

Figure 2. Block RAM PU

URAM PU

Includes one URAM, 30 adjacent CLBs (15 on each side), and the shared interconnect.

Figure 3. URAM PU

DSP PU

Includes one DSP, the five adjacent CLBs, and the shared interconnect. The PU is the corresponding DSP tile. One DSP tile includes two DSP sites.

Figure 4. DSP PU

IO PU

The I/O of the full height of the clock_region includes BITSLICE_CONTROL, BITSLICE_RX_TX, BITSLICE_TX, BUFGCE, BUFGCE_DIV, BUFGCTRL, IOB, MMCME3_ADV, PLLE3_ADV, PLL_SELECT_SITE, RIU_OR, HBM_REFCLK etc., the adjacent 60 CLBs and the shared interconnect.

Figure 5. IO PU

GTY PU

Includes a full GT quad (four GT_CHANNEL and one GT_COMMON), the adjacent 60 CLBs, 24 BUFG_GTs, 15 BUFG_GT_SYNCs, and the shared interconnect. The PU is the corresponding GTY_R_X147Y20 tile. Sites included in the tile are BUFG_GT, BUFG_GT_SYNC, GTYE4_CHANNEL, and GTYE4_COMMON. The adjacent INTF_GT tiles are automatically pulled into the routing footprint of the reconfigurable Pblock.

Figure 6. GTY PU

GTM_DUAL PU

Includes GTM_DUAL, GTM_REFCLK, 24 BUFG_GTs, 15 BUFG_GT_SYNCs, 60 CLB tiles and shared interconnect.

PCIe® PU

Includes one PCIE40E4 or PCIE4CE4, 120 adjacent CLBs (60 on each side) and the shared interconnect. The PU is the corresponding PCIe tile. It includes PCIE40E4.

Figure 7. PCIe PU

CMAC PU

Includes one CMACE4, 120 adjacent CLBs (60 on each side) and the shared interconnect.

Figure 8. CMAC PU

Interlaken PU

Includes one ILKNE4, 120 adjacent CLBs (60 on each side) and the shared interconnect.

Figure 9. Interlaken PU

CONFIG PU

Includes one CONFIG_SITE, 120 adjacent CLBs (60 on each side) and the shared interconnect.

Note: CONFIG_SITE elements cannot be reconfigured. However, you can add the CONFIG_SITE to a reconfigurable partition to get access to the CLBs. The CONFIG_SITE contains many single site resources including ICAP, STARTUP, BSCAN, FRAME_ECC, DNA_PORT, EFUSE_USR and MASTER_JTAG, and cannot be broken up further.

Figure 10. CONFIG PU

HBM BLI PU

Includes one BLI_HBM, 15 adjacent CLBs and the shared interconnect.

Figure 11. HBM BLI PU