Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) - 2024.2 English - UG909

Document ID: UG909
Release Date: 2024-12-13
Version: 2024.2 English

Introduction
Navigating Content by Design Process
Introduction to Dynamic Function eXchange
Terminology
Design Considerations
Design Requirements and Guidelines
Design Performance
Design Criteria
Dynamic Function eXchange Licensing
Common Applications
Networked Multiport Interface
Configuration by Means of Standard Bus Interface
Dynamically Reconfigurable Packet Processor
Asymmetric Key Encryption
Summary
Vivado Software Flow
Dynamic Function eXchange Commands
Synthesis
Synthesizing the Top Level
Synthesizing Reconfigurable Modules
Reading Design Modules
Method 1: Add and Link Files
Method 2: Read Netlist Design
Method 3: Open/Read Checkpoint
Method 4: Open Checkpoint/Update Design
Adding Reconfigurable Modules with Sub-Module Netlists
Method 1: Create a Single RM Checkpoint (DCP)
Method 2: Place the Sub-Module Netlists in the Same Directory as the RM's Top-Level Netlist
Reading Design Constraints
Implementation
Preserving Implementation Data
Dynamic Function eXchange Constraints and Properties
Define a Module as Reconfigurable
Create a Floorplan for the Reconfigurable Region
Floorplan in the Vivado IDE
Manage the Reconfigurable Partition Floorplan
Programmable Units
Using Visualization Scripts
Timing Constraints
Partition Pins
Context Property Examples
Apply Reset After Reconfiguration
Software Flow
Synthesis
Implementation
Incremental Compile
Reporting
Verifying Configurations
Bitstream Generation
Generating Partial Bitstreams Only
Generating Full Configuration Bitstreams Only
Generating Static-Only Bitstreams
Tcl Scripts
Nested Dynamic Function eXchange
Nested DFX Structure and Commands
Design Structure
Tcl Commands to Manage Nested DFX
pr_subdivide
pr_recombine
Implementation Design Flow
Create Reconfigurable Module Results Under A1
Create Reconfigurable Module Results Under A2
Checking Current Status
Static Design Updates
Verification Passes
Bitstream Creation
Nested DFX Design Considerations
Floorplanning
Decoupling
Dynamic Function eXchange Controller IP
Bitstream Version and Usage Compatibility
Abstract Shell for Dynamic Function eXchange
Abstract Shell Design Flow
Implementing Reconfigurable Modules in Abstract Shells
Generating Partial Bitstreams
Generating Partial Bitstreams from Full Configurations
Generating Partial Bitstreams from Abstract Shells
Device Programming Strategies
Additional Solution Details
Logical Connectivity Contents
Proprietary Design Information and Licensed IP
Abstract Shell and Nested DFX
Design Considerations
False Paths Inferred During Abstract Shell Creation
Vivado Project Flow
RTL Project Flow in the Vivado IDE
Flow Summary
Tcl Commands
Steps for Creating and Using a Dynamic Function eXchange Project
Creating a Dynamic Function eXchange Project
Defining Reconfigurable Partitions
Defining Netlist Sources
Completing the Dynamic Function eXchange Project Structure
Editing Reconfigurable Modules
Editing Configurations
Editing Configuration Runs
Adding or Modifying Reconfigurable Modules or Configurations
Adding Reconfigurable Module Constraints
Adding or Creating IP Sources
Implementing the DFX Design
Opening Post-synthesis Configurations
Generating Bitstreams
Supported/Unsupported Features
Supported Features
Unsupported Features
Known Limitations
IP Integrator Using Block Design Containers
Top-Down Flow
Bottom-Up Flow
Turning a Block Design Container into a Reconfigurable Partition
Updating Block Design Container Options
Removing a Block Design Container
Add New Design Sources to the Block Design Container
Update Port Boundaries within a BDC
Using Address Apertures
Preparing the Design for Implementation
Scoping Constraints to the Module Reference Block in the IP Integrator
Running the Dynamic Function eXchange Wizard
Editing Configurations
Editing Configuration Runs
Using Export Hardware
Supported/Unsupported Features
Supported Features
Unsupported Features
Known Issues and Limitations
Abstract Shell Project Flow
Abstract Shell Creation and Usage
Device Image Creation
Supported/Unsupported Features
Supported Features
Unsupported Features
Known Limitations and Restrictions
Design Considerations and Guidelines for All AMD Devices
Dynamic Function eXchange IP
Design Hierarchy
Dynamic Reconfiguration Using the DRP
Packing Logic
Design Instance Hierarchy
Reconfigurable Partition Interfaces
Partition Pin Placement
Active-Low Resets and Clock Enables
Decoupling Functionality
Black Boxes
Effective Approaches for Implementation
Building Up Implementation Requirements
Configuration Analysis Report
Complexity
Clocking
Timing
Summary
Managing Constraints for a DFX Design
Constraint Creation
Constraint Application
Defining Reconfigurable Partition Boundaries
Avoiding Deadlock
Design Revision Checks
Simulation and Verification
Design Considerations and Guidelines for 7 Series and Zynq Devices
Design Elements Inside Reconfigurable Modules
Global Clocking Rules
Creating Pblocks for 7 Series Devices
Automatic Adjustments for Reconfigurable Partition Pblocks
Creating Reconfigurable Partition Pblocks Manually
Using High Speed Transceivers for 7 Series Devices
Dynamic Function eXchange Design Checklist (7 Series)
Design Considerations and Guidelines for UltraScale and UltraScale+ Devices
Design Elements Inside Reconfigurable Modules
Creating Pblocks for UltraScale and UltraScale+ Devices
Automatic Adjustments for PU on Pblocks
Sharing Configuration Frames between RP and Static Logic
Expansion of CONTAIN_ROUTING Area
UltraRAM Behavior
Floorplanning Rules for Clocks Inside an RP
Global Clocking Rules
I/O Rules
Using High Speed Transceivers for UltraScale and UltraScale+ Devices
Dynamic Function eXchange Checklist for UltraScale and UltraScale+ Device Designs
Recommended Floorplanning Constraints
Reduce the Number of Partition Pins
Recommended Netlist Structure at the DFX Boundary for Maximum PPLOC Reduction
Avoid RP to RP Direct Paths
Avoid Multiple RPs Driving Same Static Leaf Cell
Replicate Static Register Driving Multiple RPs
Register Inputs and Outputs of RMs
Reduce Bleed Over of Static Nets to the Reconfigurable Pblocks
Make Pblocks as Rectangular as Possible to Avoid Unroutability at the Edges
Considerations for Static Pblocks with CONTAIN_ROUTING Enabled
Keep Routability as a Factor in Utilization
Reduce the Number of Unique Control Sets
Reduce the Detour Due to Hold Violations
Exclude Containment Requirement for Nets
Avoid Disjoint Pblocks Whenever Possible for UltraScale and UltraScale+ Devices
Design Considerations and Guidelines for Versal Devices
DFX Design Migration from Standard Flow to Advanced Flow
Design Elements Inside Reconfigurable Modules
I/O Rules
Floorplanning for Versal Devices
Floorplanning with SNAPPING_MODE
Clock Region Sharing Between Multiple Reconfigurable Pblocks
Floorplanning Visualization
BLI Floorplan Alignment
Special Considerations for XPIO Usage
Expanded Routing
Clocking Resources
Floorplanning Design Rule Checks
Global Clocking Rules
Major Enhancements for Clocking in Versal Device DFX Designs Compared to UltraScale+ Devices
Known Restrictions for Clocking in Versal Device DFX Designs
Divided Outputs on MBUFGCE Primitives Not Allowed for Boundary Clock Nets
Restrictions in Clock Resource Usage Due to Clock Tile Splitting
Clocking Instances Can Be Prohibited Due to Expanded Routing Footprints
Network on Chip
NoC Topologies Supported in the DFX Design Flow
Design Entry Methodology for DFX Designs that use NoC
RTL Modular NoC Flow
Virtual NoC Interface
Scope the DFX Region NoC Constraints
Drawing an Analogy to Timing Constraints
Defining Aperture for DFX Region Peripherals
Ownership Concept
Static Region Ownership and Virtual NoC Interfaces
Dynamic Region Ownership and Virtual NoC Interfaces
Modular NoC DFX Tutorials
IP Integrator Block Design Container Flow
Inter-NoC Interconnect (INI)
INI Ownership Concept
Static Region Ownership and INI
Dynamic Region Ownership and INI
Considerations with IP Integrator BDC DFX Flow
IP Integrator Block Design Container DFX Tutorials
NoC Path Ownership in the DFX Design Flow
NoC Paths Located Entirely Within a Specific Region
NoC Paths with NMU and NSU in Separate Regions
Network-1: NMU in Static Region Accessing NSU in Dynamic Region
Network-2: NMU in Dynamic Region Accessing NSU in Static Region
DRCs for NoC Paths Across DFX Boundaries
Greybox Support for NoC
NoC Traffic Impact During Reconfiguration
DFX for SSI Technology Versal Devices
Multi-SLR Dynamic Regions
Static Routing Across SLR Boundaries
Hardened DDR Memory Controllers
Logical Decoupling
Logical Decoupling at the PL Boundary
Logical Decoupling in the NoC
Logical Decoupling at the PS-PL Interface
Debugging Versal Device DFX Designs
Adding Debug Cores for Versal Devices
Instantiation
Insertion
Setting Up Inserted Debug Cores
Recommended Floorplanning Constraints
Range Only the Required Physical Sites within HSR Pblock Rectangles for Designs with Two RPs
Avoid Disjoint Pblocks Whenever Possible for Versal Devices
Create Disjoint Pblocks for a Reconfigurable Partition
Using Report DFX Summary
Usage
Design Configuration
Design Utilization Summary
Design Clock Utilization Summary
SLL Summary
PPLOC Summary
RP Details
Shared Tile Reason
Configuring the Device
Configuration Modes
Bitstream Type Definitions
Full Configuration Bitstreams
Partial Bitstreams
Downloading a Partial BIT File
Blanking Bitstreams
Clearing Bitstreams
Dynamic Function eXchange through ICAP for Zynq Devices
Tandem Configuration and Dynamic Function eXchange
Tandem Configuration and Devices
Formatting BIN Files for Delivery to Internal Configuration Ports
Summary of BIT Files for UltraScale Devices
System Design for Configuring an FPGA
Partial BIT File Integrity
Configuration Frames
Configuration Time
Configuration Debugging
Using Vivado Debug Cores
Configuration Solutions for Versal Devices
Partial PDI Creation and Details
Supported Boot Modes
Secure Boot Modes
Design Version Compatibility Checks
Tandem Configuration and PCIe
Reconfiguration via U-Boot
Reconfiguration via Linux
Programming Image Compression
NoC Clock Gating Issue
Segmented Configuration
Known Issues and Limitations
Known Issues
Known Limitations
Hierarchical Design Flows
Supported Devices
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Training Resources
Revision History
Please Read: Important Legal Notices

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