Versal devices provide more capability for you to debug your designs in hardware. This includes JTAG based debug as well as high speed debug protocol (HSDP) using GT transceivers or PCI® Express. For debugging DFX designs in Versal, you must take additional steps to ensure proper connectivity to debug cores like ILA, VIO that are contained within both the static region and the reconfigurable partition. For all DFX designs, you should instantiate an instance of the AXI Debug Hub IP with connectivity to the Versal CIPS IP inside each design partition, both static and reconfigurable, that might contain debug cores. The AXI Debug Hub IP instantiated in each design partition is used by the debug flow for the connectivity infrastructure to all debug cores (ILA, VIO, etc) contained within that design partition.
AMD recommends using NoC INI
(Inter-NoC-Interconnect) interface across static-RM boundary to communicate to AXI Debug
Hub in reconfigurable partition. This is preferred because isolation is built into the
NoC architecture.
Note: Accessing the
AXI Debug Hub in an RP across a PL based DFX decoupler requires manual intervention.
Contact AMD for more information.