Synthesizing the Top Level - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-05-30
Version
2024.1 English

You must have a top-level netlist with a black box for each reconfigurable partition (RP). This requires the top-level synthesis to have module or entity declarations for the partitioned instances, but no logic; the module is empty.

The top-level synthesis infers or instantiates I/O buffers on all top level ports. For more information on controlling buffer insertion, see the Setting a Bottom-Up Out-of-Context Flow topic in the Vivado Design Suite User Guide: Synthesis (UG901).

synth_design -flatten_hierarchy rebuilt -top <top_module_name> -part <part>