Vivado Software Flow - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

The AMD Vivado™ Dynamic Function eXchange (DFX) design flow is similar to a standard design flow, with some notable differences. The implementation software automatically manages the low-level details to meet silicon requirements. You must provide guidance to define the design structure and floorplan. The following steps summarize processing a DFX design:

  1. Synthesize the static and reconfigurable modules (RM) separately. See Synthesis for more information.
  2. Create physical constraints (Pblocks) to define the reconfigurable regions. See Create a Floorplan for the Reconfigurable Region for more information.
  3. Set the HD.RECONFIGURABLE property on each reconfigurable partition (RP). See Define a Module as Reconfigurable for more information.
  4. Implement a complete design (static and one RM per RP) in context. See Implementation for more information.
  5. Save a design checkpoint for the full routed design. See Implementation for more information.
  6. Remove RMs from this design and save a static-only design checkpoint. See Implementation for more information.
  7. Lock the static placement and routing. See Preserving Implementation Data for more information.
  8. Add new RMs to the static only design and implement this new configuration, saving a checkpoint for the full routed design.
  9. Repeat Step 8 until all RMs are implemented.
  10. Run a verification utility (pr_verify) on all configurations. See Verifying Configurations for more information.
  11. Create bitstreams for each configuration. See Bitstream Generation for more information.