Interface points called partition pins are automatically created within the Pblock ranges defined for the RP. These virtual I/O are established within interconnect tiles as the anchor points that remain consistent from one module to the next. No physical resources such as LUTs or flip-flops are required to establish these anchor points, and no additional delay is incurred at these points.
The placer chooses locations based on source and loads and timing requirements, but you can specify these locations as well. The following constraints can be applied to influence partition pin placement.
| Command/Property Name | Description |
|---|---|
HD.PARTPIN_LOCS
|
Used to define a specific interconnect tile (INT) for the specified port to be
routed. Overrides an Do not use this property on clock ports, as this assumes local routing for the clock. Do not use this property on dedicated connections. |
HD.PARTPIN_RANGE
|
Used to define a range of component sites (SLICE, DSP, block RAM) or interconnect tiles (INT) that can be used to route the specified port(s). The value is automatically calculated based on Pblock range if no user-defined |