Partition Pins - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

Interface points called partition pins are automatically created within the Pblock ranges defined for the RP. These virtual I/O are established within interconnect tiles as the anchor points that remain consistent from one module to the next. No physical resources such as LUTs or flip-flops are required to establish these anchor points, and no additional delay is incurred at these points.

The placer chooses locations based on source and loads and timing requirements, but you can specify these locations as well. The following constraints can be applied to influence partition pin placement.

Table 1. Context Properties
Command/Property Name Description
HD.PARTPIN_LOCS

Used to define a specific interconnect tile (INT) for the specified port to be routed. Overrides an HD.PARTPIN_RANGE value. Affects placement and routing of logic on both sides of the RP boundary.

Do not use this property on clock ports, as this assumes local routing for the clock.

Do not use this property on dedicated connections.

HD.PARTPIN_RANGE

Used to define a range of component sites (SLICE, DSP, block RAM) or interconnect tiles (INT) that can be used to route the specified port(s).

The value is automatically calculated based on Pblock range if no user-defined HD.PARTPIN_RANGE value exists.

Note: The PARTPIN_SPREADING property in Table 1, can also be used to affect Partition Pins, but is applied at the Pblock level.

Context Property Examples

  • set_property HD.PARTPIN_LOCS INT_R_X4Y153 [get_pins <hier/pin>]
  • set_property HD.PARTPIN_RANGE SLICE_X4Y153:SLICE_X5Y157 [get_pins <hier/pins>]

get_pins should use the full hierarchical path to the pin or pins to be constrained on the partition interface. get_ports can also be used, but the reference must be scoped to the proper level of hierarchy. Instance names for interconnect tile sites can be seen in the Device View with the Routing Resources enabled.

Note: The HD.PARTPIN_RANGE is automatically set during place_design if no user-defined value is found. Once the value is set, it will not be reset during interactive place and route, such as making experimental changes to the RP Pblocks and running place_design -unplace. In this case, the HD.PARTPIN_RANGE and HD.PARTPIN_LOCS need to be reset manually if Pblock adjustments are made. The properties can be reset like most properties.

The following Tcl proc can be useful when doing this kind of interactive floorplanning on DFX designs:

################################################## 
Proc to unroute, uplace, and reset HD.PARTPIN_* 
#################################################
proc pr_unplace {} {
route_design -unroute
place_design -unplace
set cells [get_cells -quiet -hier -filter HD.RECONFIGURABLE]
foreach cell $cells {
reset_property HD.PARTPIN_LOCS [get_pins $cell/*]
reset_property HD.PARTPIN_RANGE [get_pins $cell/*]
}
}

Partition pin information can be obtained from placed or routed designs by using the get_pplocs command. Use either the -nets or -pins option to focus the response to a particular RP or interface pin.

get_pplocs -nets <args> -pins <args> [-count] [-unlocked] [-locked] [-level <arg>] [-quiet] [-verbose]
Table 2. get_pplocs Options
Name Description
-nets List of nets to report its PPLOCs.
-pins List of pins to report its PPLOCs.
[-count] Count number of PPLOCs; Do not report PPLOC or node names.
[-unlocked] Report unlocked/unfixed PPLOCs only.
[-locked] Report locked/fixed PPLOCs only; use -level to specify locked level.
[-level] Specify locked level.
[-quiet] Ignore command errors.
[-verbose] Suspend message limits during command execution.

Example:

get_pplocs -pins [get_pins u_count/*]

In UltraScale or UltraScale+ designs, not all interface ports receive a partition pin. With the routing expansion feature, as explained in Expansion of CONTAIN_ROUTING Area, some interface nets are completely contained within the expanded region. When this happens, no partition pin is inserted; the entire net, including the source and all loads, is contained within the area captured by the partial bit file. Rather than pick an unnecessary intermediate point for the route, the entire net is rerouted, giving the Vivado tools the flexibility to pick an optimal solution.