BLI Floorplan Alignment - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

In Versal devices, boundary logic interfaces (BLI) tiles are additional register stages available for signals going in and out of programmable logic (PL) to and from XPIO logic resources. The BLI register stages help optimize the timing of interfaces.

Based on the location, a BLI tile can be used by multiple sites:

  • XPHY and XPIOLOGIC sites in a XPIO_NIBBLE tile.
  • DDRMC.
  • XPLL sites in a CMT_XPLL tile.
  • DPLL sites in a CMT_DPLL tile.
  • BUFGCE sites in a CLK_REBUF_BUFGS_HSR_CORE tile.
  • MMCM sites in a CMT_MMCM tile.

Because the BLIs are aligned geometrically to each of the site types that use the BLI, the DFX flow automatically pulls the BLIs based on the tiles in the range of Pblocks. Following are some of the rules associated with adding BLI ranges to the reconfigurable Pblock:

  • BLI tiles can be independently added to the reconfigurable Pblock range, even though none of the tiles mentioned above are added in the Pblock range.
  • If an XPIO tile is ranged into an RP, the connected BLI will be pulled into the placement footprint.
  • If clocking resources like BUFG or MMCM are ranged in a reconfigurable Pblock, the connected BLI will be pulled into the placement footprint by the tool.
  • If AIE_PL or AIE_NOC sites are ranged in a reconfigurable Pblock, the connected BLI will be pulled into the RP Pblock range automatically.
  • If a conflict is observed that breaks the automatic pulling of BLI ranges, a DRC is flagged. This can happen when there are two tiles trying to use the same BLI, but those two tiles happen to be in two separate reconfigurable partitions. The DRC message also provides the resolution to remove the corresponding tile from the Pblock to avoid the conflict.

In the following figure, the CMT_MMCM tile (marked in magenta) is present in pblock_rp1rm1 and the XPIO tile (marked in green) is present in pblock_rp2rm1. The BLI tile (marked in red) is added in the placement footprint of both the RPs due to the HSR routing (highlighted in yellow).

Figure 1. BLI Sharing and Floorplan Alignment

This triggers the following DRC error, because the BLI is being shared by tiles of two different RPs.

HDPR-39- Error
Reconfigurable Pblocks must not lead to overlap of footprints in same frame tile  
Overlapping tile : BLI_CLE_BOT_CORE_1_X29Y0 
	- Is in PLACEMENT footprint of reconfigurable pblock 'pblock_rp1rm1'
	  Footprint Expansion Path : 
		 - BLI_CLE_BOT_CORE_1_X29Y0 tile in PLACEMENT footprint  for HSR_ROUTING
		 - CMT_MMCM_X14Y0 tile in PBLOCK
	- Is in PLACEMENT footprint of reconfigurable pblock 'pblock_rp2rm1' 
	  Footprint Expansion Path : 
		 - BLI_CLE_BOT_CORE_1_X29Y0 tile in PLACEMENT footprint  for HSR_ROUTING
		 - XPIO_NIBBLE_SC_X29Y0 tile in PBLOCK
Resolution : Resize pblock to avoid overlaps in footprint using following tcl commands
	 * resize_pblock
	 * get_sites -of [get_tiles <tile in PBLOCK>]

You can remove one of the shared tiles to resolve the issue reported by the DRC and avoid having the same BLI shared by two RPs. You must resize the Pblocks to avoid overlaps. One resolution is to remove the conflicting CMT_MMCM tile from pblock_rp1rm1 and add the adjacent CMT_MMCM tile:

resize_pblock pblock_rp1rm1 -remove [get_sites -of_objects [get_tiles CMT_MMCM_X14Y0]]

resize_pblock pblock_rp1rm1 -add [get_sites -of_objects [get_tiles CMT_MMCM_X4Y0]]

To visualize the overlapping tiles, you can use the following commands to highlight and mark the placement footprint of the two RPs:

highlight_objects -color yellow [get_dfx_footprint -place -of_objects [get_cells <RP1_cellname>]]

mark_objects -color blue [get_dfx_footprint -place -of_objects [get_cells <RP2_cellname>]]

In the following example, the overlapping tiles are yellow and blue (shown in the red circle).

Figure 2. Overlapping Tiles Example

Special Considerations for XPIO Usage

When including XPIO within a reconfigurable partition, the reconfigurable module with the greatest amount of usage must be included in the parent configuration. Any XPIO sites that remain unused in that initial configuration are tied to ground to meet silicon requirements. These tie-offs are considered static and remain for subsequent configurations, which means these sites are unavailable for RMs in child configurations. The Vivado tools automatically insert PROHIBIT constraints on unusable sites. Attempts to assign I/Os to these sites result in an error. For example:
ERROR: [DRC HDPR-29] Reconfigurable logic illegally placed: Reconfigurable logic 'design_top/pl_top/instance_1' is placed at site 'IOB_X52Y0' outside reconfigurable Pblock 'my_dynamic_pblock'.

The recommended strategy is to build the worst case (greatest usage), which is declared in the parent configuration so all subsequent RMs have equal or lesser usage. In hardware, partial images can be delivered in any order.