Floorplanning Design Rule Checks - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

The floorplanning design rule checks (DRCs) ensure that floorplanning guidelines for DFX designs were followed. DRC violations might be due to unsupported Pblock shapes or due to overlapping Pblocks caused by footprint expansions.

The overlapping Pblock DRC messages provide the following information:

  • Rule that was violated.
  • Overlapping tile.
  • Reason for the tile to be added to the RP placement, routing, or clocking footprint.
  • Suggested resolution of resizing the reconfigurable Pblocks to avoid the overlap.

The DRC messages indicate the reason for the footprint expansion as follows:

Programmable Unit (PU)
Expanded to include all the programmable units of the tiles that belong to the RP Pblock.
HSR_ROUTING
Expanded to add BLI tiles required for connecting the HSR tiles (CMT_MMCM, CMT_DPLL, and CMT_REBUF_BUFGS_HSR_CORE) to the fabric.
FRAME_ALIGNMENT
Expanded to include all tiles programmed by the reconfigurable frame to the same Pblock.
CLK_REBUF_EXPANSION
Collected the BUFG tiles on bi-directional clock nodes in HSR region and included the tiles in the expanded RP footprint.
PBLOCK_CONSTRAINT
Collected the list of tiles from user-specified Pblock constraints and added the tiles to the expanded Pblock footprint.