The HLS compilation mode provides access to numerous features for the
development, optimization, analysis, and export of Vitis kernels (.xo) or Vivado IP
(.xci) files. The HLS mode can be reached by using the following command:
v++ -c --mode hls -h [options] <input_files...>The HLS compilation options should be entered into a configuration file for
use with the v++ command using the --config option. The HLS options should be placed under a
section head of [HLS] in the config file. For example
the following config file specifies the part, the source file, the test bench files, and
the flow target. part is not specified under the
[HLS] header because this is a general option for
the v++ compiler.
part=xcvu11p-flga2577-1-e
[hls]
clock=8
flow_target=vitis
syn.file=../../src/dct.cpp
syn.top=dct
tb.file=../../src/out.golden.dat
tb.file=../../src/in.dat
tb.file=../../src/dct_test.cpp
tb.file=../../src/dct_coeff_table.txt
syn.output.format=xo
clock_uncertainty=15%
Tip: To use the HLS config options on the
v++ command line you can simply begin the command
name with --hls. For instance, to specify the
flow_target from the command line use --hls.flow_target. The HLS mode command options are described in the following sections.