The Vitis unified IDE provides live waveform-based HDL debugging in the hardware emulation mode. The waveform is opened in the Vivado waveform viewer which should be familiar to Vivado logic simulation users. The Vitis IDE lets you display kernel interfaces, internal signals, and includes debug controls such as restart, HDL breakpoints, as well as HDL code lookup and waveform markers. In addition, it provides top-level DDR data transfers (per bank) along with kernel-specific details including compute unit stalls, loop pipeline activity, and data transfers. For details, see Waveform View and Live Waveform Viewer.
If the live waveform viewer is activated, the waveform viewer automatically opens when running the executable. By default, the waveform viewer shows all interface signals and the following debug hierarchy:
- Memory Data Transfers
- Shows data transfers from all compute units funnel through these
interfaces.Tip: These interfaces could be a different bit width from the compute units. If so, then the burst lengths would be different. For example, a burst of sixteen 32-bit words at a compute unit would be a burst of one 512-bit word at the OCL master.
- Kernel <kernel name><workgroup size> Compute Unit<CU name>
- Kernel name, workgroup size, and compute unit name.
- CU Stalls (%)
- This shows a summary of stalls for the entire CU. A bus of all lowest-level stall signals is created, and the bus is represented in the waveform as a percentage (%) of those signals that are active at any point in time.
- Data Transfers
- This shows the data transfers for all AXI masters on the CU.
- User Functions
- This lists all of the functions within the hierarchy of the CU.
- Function: <function name>
- This is the function name.
- Dataflow/Pipeline Activity
- This shows the function-level loop dataflow/pipeline signals for a CU.
- Function Stalls
- This lists the three stall signals within this function.
- Function I/O
- This lists the I/O for the function. These I/O are of protocol
-m_axi,ap_fifo,ap_memory, orap_none.