In the Vitis core development kit,
Alveo Data Center acceleration cards and custom
embedded platforms provide a foundation for designs. Targeted devices can include
AMD Versal™
adaptive SoCs, Zynq UltraScale+ MPSoCs, Kria SOMs,
or AMD UltraScale+™
FPGAs. These devices contain a
programmable logic (PL) region that loads and executes a device binary (.xclbin) file that contains and connects PL kernels as
compiled object (.xo) files and can also contain
AI Engine graphs.
Extensible Alveo acceleration cards
and custom embedded platforms contain one or more interfaces to global memory (DDR or
HBM), and optional streaming interfaces connected to other resources
such as AI Engines and external I/O. PL kernels can
access data through global memory interfaces (m_axi) or
streaming interfaces (axis). The memory interfaces of
PL kernels must be connected to memory interfaces of the extensible platform. The
streaming interfaces of PL kernels can be connected to any streaming interfaces of the
platform, of other PL kernels, or of the AI Engine array. Both memory-based and streaming connections are
defined through Vitis linking options, as described
in Linking the System.
Multiple kernels (.xo) can be implemented in the PL region of the AMD device binary (.xclbin), allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances, or compute units of a kernel is programmable up to 31, and determined by linking options specified when building the device binary.
For Versal devices the .xclbin file can also contains the compiled AI Engine graph application (libadf.a). The graph application consists of nodes and edges where nodes
represent compute kernel functions, and edges represent data connections. Kernel
functions are the fundamental building blocks of an ADF graph application. Kernels
operate on data streams, consuming input blocks of data and producing output blocks of
data. The libadf.a and PL kernels (.xo) are linked with the target platform (.xpfm) to define the hardware design. The AI Engine can be driven by PL kernels through axis interfaces. The AI Engine can also be controlled through the Arm processor (PS) via runtime parameters (RTP) in the graph and GMIO on
Versal adaptive SoC devices. Refer to
AI
Engine Tools and Flows User Guide (UG1076) for more information.