Output Directories of v++ -c --mode hls - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

The directory structure generated by the v++ -c --mode hls command has been organized to let you easily find and access files from the project.

The example directory provided below results from the following command lines:

v++ -c --mode hls --config ./workDCT/dct/hls_config.cfg --work_dir newDCT

Where hls_config.cfg.cfg file defines the following options:

part=xczu7ev-ffvc1156-2-e

[hls]
syn.file=/reference-files/src/dct.cpp
tb.file=/reference-files/src/out.golden.dat
tb.file=/reference-files/src/in.dat
tb.file=/reference-files/src/dct_test.cpp
tb.file=/reference-files/src/dct_coeff_table.txt
syn.top=dct
clock=8ns
clock_uncertainty=12%
csim.code_analyzer=1
csim.clean=true
flow_target=vitis
package.output.format=xo
syn.directive.pipeline=dct_2d II=4
package.output.syn=1
syn.compile.pipeline_loops=6

An example of the temp_dir output of the v++ link command follows:

newDCT
├── hls
│   ├── config.cmdline
│   ├── hls_data.json
│   ├── impl
│   │   ├── misc
│   │   │   ├── drivers
│   │   │   │   └── dct_v1_0
│   │   │   │       ├── data
│   │   │   │       │   ├── dct.mdd
│   │   │   │       │   ├── dct.tcl
│   │   │   │       │   └── dct.yaml
│   │   │   │       └── src
│   │   │   │           ├── CMakeLists.txt
│   │   │   │           ├── Makefile
│   │   │   │           ├── xdct.c
│   │   │   │           ├── xdct.h
│   │   │   │           ├── xdct_hw.h
│   │   │   │           ├── xdct_linux.c
│   │   │   │           └── xdct_sinit.c
│   │   │   └── logo.png
│   │   ├── verilog
│   │   │   ├── dct_ama_addmuladd_18s_16s_13ns_29ns_29_4_1.v
│   │   │   ├── dct_ama_submuladd_16s_16s_12ns_29s_29_4_1.v
│   │   │   ├── dct_ama_submuladd_16s_16s_13ns_29s_29_4_1.v
│   │   │   ├── dct_ama_submuladd_18s_16s_14ns_29ns_29_4_1.v
│   │   │   ├── dct_buf_2d_in_RAM_AUTO_1R1W_memcore.v
│   │   │   ├── dct_buf_2d_in_RAM_AUTO_1R1W.v
│   │   │   ├── dct_buf_2d_out_RAM_AUTO_1R1W_memcore.v
│   │   │   ├── dct_buf_2d_out_RAM_AUTO_1R1W.v
│   │   │   ├── dct_control_s_axi.v
│   │   │   ├── dct_dct_2d.v
│   │   │   ├── dct_entry_proc.v
│   │   │   ├── dct_fifo_w64_d6_S.v
│   │   │   ├── dct_flow_control_loop_pipe_sequential_init.v
│   │   │   ├── dct_gmem_m_axi.v
│   │   │   ├── dct_mac_muladd_16s_14ns_29ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_16s_14ns_29s_29_4_1.v
│   │   │   ├── dct_mac_muladd_16s_15s_13ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_16s_15s_29ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_16s_15s_29s_29_4_1.v
│   │   │   ├── dct_mac_muladd_17s_12ns_13ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_17s_12ns_29s_29_4_1.v
│   │   │   ├── dct_mac_muladd_17s_13ns_13ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_17s_13ns_29s_29_4_1.v
│   │   │   ├── dct_mac_muladd_18s_13ns_13ns_29_4_1.v
│   │   │   ├── dct_mac_muladd_18s_14ns_13ns_29_4_1.v
│   │   │   ├── dct_mul_16s_15ns_29_1_1.v
│   │   │   ├── dct_mul_16s_15s_29_1_1.v
│   │   │   ├── dct_mul_17s_13ns_29_1_1.v
│   │   │   ├── dct_mul_17s_14ns_29_1_1.v
│   │   │   ├── dct_read_data_Pipeline_RD_Loop_Col.v
│   │   │   ├── dct_read_data.v
│   │   │   ├── dct_sparsemux_17_3_16_1_1.v
│   │   │   ├── dct.v
│   │   │   ├── dct_write_data_Pipeline_WR_Loop_Col.v
│   │   │   └── dct_write_data.v
│   │   └── vhdl
│   │       ├── dct_ama_addmuladd_18s_16s_13ns_29ns_29_4_1.vhd
│   │       ├── dct_ama_submuladd_16s_16s_12ns_29s_29_4_1.vhd
│   │       ├── dct_ama_submuladd_16s_16s_13ns_29s_29_4_1.vhd
│   │       ├── dct_ama_submuladd_18s_16s_14ns_29ns_29_4_1.vhd
│   │       ├── dct_buf_2d_in_RAM_AUTO_1R1W_memcore.vhd
│   │       ├── dct_buf_2d_in_RAM_AUTO_1R1W.vhd
│   │       ├── dct_buf_2d_out_RAM_AUTO_1R1W_memcore.vhd
│   │       ├── dct_buf_2d_out_RAM_AUTO_1R1W.vhd
│   │       ├── dct_control_s_axi.vhd
│   │       ├── dct_dct_2d.vhd
│   │       ├── dct_entry_proc.vhd
│   │       ├── dct_fifo_w64_d6_S.vhd
│   │       ├── dct_flow_control_loop_pipe_sequential_init.vhd
│   │       ├── dct_gmem_m_axi.vhd
│   │       ├── dct_mac_muladd_16s_14ns_29ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_16s_14ns_29s_29_4_1.vhd
│   │       ├── dct_mac_muladd_16s_15s_13ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_16s_15s_29ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_16s_15s_29s_29_4_1.vhd
│   │       ├── dct_mac_muladd_17s_12ns_13ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_17s_12ns_29s_29_4_1.vhd
│   │       ├── dct_mac_muladd_17s_13ns_13ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_17s_13ns_29s_29_4_1.vhd
│   │       ├── dct_mac_muladd_18s_13ns_13ns_29_4_1.vhd
│   │       ├── dct_mac_muladd_18s_14ns_13ns_29_4_1.vhd
│   │       ├── dct_mul_16s_15ns_29_1_1.vhd
│   │       ├── dct_mul_16s_15s_29_1_1.vhd
│   │       ├── dct_mul_17s_13ns_29_1_1.vhd
│   │       ├── dct_mul_17s_14ns_29_1_1.vhd
│   │       ├── dct_read_data_Pipeline_RD_Loop_Col.vhd
│   │       ├── dct_read_data.vhd
│   │       ├── dct_sparsemux_17_3_16_1_1.vhd
│   │       ├── dct.vhd
│   │       ├── dct_write_data_Pipeline_WR_Loop_Col.vhd
│   │       └── dct_write_data.vhd
│   ├── kernel.xml
│   └── syn
│       ├── report
│       │   ├── csynth_design_size.rpt
│       │   ├── csynth_design_size.xml
│       │   ├── csynth.rpt
│       │   ├── csynth.xml
│       │   ├── dct_2d_csynth.rpt
│       │   ├── dct_2d_csynth.xml
│       │   ├── dct_csynth.rpt
│       │   ├── dct_csynth.xml
│       │   ├── entry_proc_csynth.rpt
│       │   ├── entry_proc_csynth.xml
│       │   ├── read_data_csynth.rpt
│       │   ├── read_data_csynth.xml
│       │   ├── read_data_Pipeline_RD_Loop_Col_csynth.rpt
│       │   ├── read_data_Pipeline_RD_Loop_Col_csynth.xml
│       │   ├── write_data_csynth.rpt
│       │   ├── write_data_csynth.xml
│       │   ├── write_data_Pipeline_WR_Loop_Col_csynth.rpt
│       │   └── write_data_Pipeline_WR_Loop_Col_csynth.xml
│       ├── verilog
│       │   ├── dct_ama_addmuladd_18s_16s_13ns_29ns_29_4_1.v
│       │   ├── dct_ama_submuladd_16s_16s_12ns_29s_29_4_1.v
│       │   ├── dct_ama_submuladd_16s_16s_13ns_29s_29_4_1.v
│       │   ├── dct_ama_submuladd_18s_16s_14ns_29ns_29_4_1.v
│       │   ├── dct_buf_2d_in_RAM_AUTO_1R1W_memcore.v
│       │   ├── dct_buf_2d_in_RAM_AUTO_1R1W.v
│       │   ├── dct_buf_2d_out_RAM_AUTO_1R1W_memcore.v
│       │   ├── dct_buf_2d_out_RAM_AUTO_1R1W.v
│       │   ├── dct_control_s_axi.v
│       │   ├── dct_dct_2d.v
│       │   ├── dct_entry_proc.v
│       │   ├── dct_fifo_w64_d6_S.v
│       │   ├── dct_flow_control_loop_pipe_sequential_init.v
│       │   ├── dct_gmem_m_axi.v
│       │   ├── dct_mac_muladd_16s_14ns_29ns_29_4_1.v
│       │   ├── dct_mac_muladd_16s_14ns_29s_29_4_1.v
│       │   ├── dct_mac_muladd_16s_15s_13ns_29_4_1.v
│       │   ├── dct_mac_muladd_16s_15s_29ns_29_4_1.v
│       │   ├── dct_mac_muladd_16s_15s_29s_29_4_1.v
│       │   ├── dct_mac_muladd_17s_12ns_13ns_29_4_1.v
│       │   ├── dct_mac_muladd_17s_12ns_29s_29_4_1.v
│       │   ├── dct_mac_muladd_17s_13ns_13ns_29_4_1.v
│       │   ├── dct_mac_muladd_17s_13ns_29s_29_4_1.v
│       │   ├── dct_mac_muladd_18s_13ns_13ns_29_4_1.v
│       │   ├── dct_mac_muladd_18s_14ns_13ns_29_4_1.v
│       │   ├── dct_mul_16s_15ns_29_1_1.v
│       │   ├── dct_mul_16s_15s_29_1_1.v
│       │   ├── dct_mul_17s_13ns_29_1_1.v
│       │   ├── dct_mul_17s_14ns_29_1_1.v
│       │   ├── dct_read_data_Pipeline_RD_Loop_Col.v
│       │   ├── dct_read_data.v
│       │   ├── dct_sparsemux_17_3_16_1_1.v
│       │   ├── dct.v
│       │   ├── dct_write_data_Pipeline_WR_Loop_Col.v
│       │   └── dct_write_data.v
│       └── vhdl
│           ├── dct_ama_addmuladd_18s_16s_13ns_29ns_29_4_1.vhd
│           ├── dct_ama_submuladd_16s_16s_12ns_29s_29_4_1.vhd
│           ├── dct_ama_submuladd_16s_16s_13ns_29s_29_4_1.vhd
│           ├── dct_ama_submuladd_18s_16s_14ns_29ns_29_4_1.vhd
│           ├── dct_buf_2d_in_RAM_AUTO_1R1W_memcore.vhd
│           ├── dct_buf_2d_in_RAM_AUTO_1R1W.vhd
│           ├── dct_buf_2d_out_RAM_AUTO_1R1W_memcore.vhd
│           ├── dct_buf_2d_out_RAM_AUTO_1R1W.vhd
│           ├── dct_control_s_axi.vhd
│           ├── dct_dct_2d.vhd
│           ├── dct_entry_proc.vhd
│           ├── dct_fifo_w64_d6_S.vhd
│           ├── dct_flow_control_loop_pipe_sequential_init.vhd
│           ├── dct_gmem_m_axi.vhd
│           ├── dct_mac_muladd_16s_14ns_29ns_29_4_1.vhd
│           ├── dct_mac_muladd_16s_14ns_29s_29_4_1.vhd
│           ├── dct_mac_muladd_16s_15s_13ns_29_4_1.vhd
│           ├── dct_mac_muladd_16s_15s_29ns_29_4_1.vhd
│           ├── dct_mac_muladd_16s_15s_29s_29_4_1.vhd
│           ├── dct_mac_muladd_17s_12ns_13ns_29_4_1.vhd
│           ├── dct_mac_muladd_17s_12ns_29s_29_4_1.vhd
│           ├── dct_mac_muladd_17s_13ns_13ns_29_4_1.vhd
│           ├── dct_mac_muladd_17s_13ns_29s_29_4_1.vhd
│           ├── dct_mac_muladd_18s_13ns_13ns_29_4_1.vhd
│           ├── dct_mac_muladd_18s_14ns_13ns_29_4_1.vhd
│           ├── dct_mul_16s_15ns_29_1_1.vhd
│           ├── dct_mul_16s_15s_29_1_1.vhd
│           ├── dct_mul_17s_13ns_29_1_1.vhd
│           ├── dct_mul_17s_14ns_29_1_1.vhd
│           ├── dct_read_data_Pipeline_RD_Loop_Col.vhd
│           ├── dct_read_data.vhd
│           ├── dct_sparsemux_17_3_16_1_1.vhd
│           ├── dct.vhd
│           ├── dct_write_data_Pipeline_WR_Loop_Col.vhd
│           └── dct_write_data.vhd
├── logs
│   ├── hls_compile.log
│   ├── newDCT.steps.log
│   └── xcd.log
├── newDCT.hlscompile_summary
├── reports
│   ├── hls_compile.rpt
│   └── v++_compile_newDCT_guidance.html
└── vitis-comp.json