The use cases include the following:
- Emulate AXI4 memory map Master/Slave through an external process such as Python/C++. This can help you with emulating design with quick design time of AXI4 Master/Slave without investing resources in developing AXI4 Master.
- Chip-to-chip connection between two FPGAs can be emulated with AXI4 memory map Interprocess communication.