AXI4 Memory Map External Traffic through Python/C++ - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

The AXI4 memory map external traffic which is supported only for hardware emulation has the following specifications:

  • Only transaction-level granularity is supported.
  • Re-ordering of transactions is not supported.
  • Parallel Read, Write transactions are not supported (transactions will be serialized).
  • Unaligned transactions are not supported.

The following figure shows the high-level design.

Figure 1. AXI4 Memory Map External Traffic Design