Interpreting Data in the Waveform Views - 2024.1 English

The following image shows the Waveform view:

The Waveform and Live Waveform views are organized hierarchically for easy navigation.

• The Waveform view is based on the actual waveforms generated during hardware emulation (Kernel Trace). This allows the viewer to descend all the way down to the individual signals responsible for the abstracted data. However, because the Waveform view is generated from the post-processed data, no additional signals can be added to the report, and some of the runtime analysis cannot be visualized, such as DATAFLOW transactions.
• The Live Waveform viewer is displaying the Vivado logic simulator (xsim) run, so you can add extra signals and internals of the register transfer (RTL) design to the live view. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for information on working with the Waveform viewer.

The hierarchy of the Waveform and Live Waveform views include the following:

HLS Process Summary

• Hierarchical view of processes and their sub-processes corresponding to the user functions in CU
• Entry for each kernel instance which has processes modeling user function in it (entries can be unfolded to show the processes in it)
• Handshake transactions on all the processes corresponding to user-functions
• Both dataflow and non-dataflow/non-piplelined processes
• The transactions on the processes including stalls, are shown using the corresponding protocol analyzer instance
• Allows you to get an overview about the usage of the individual processes over the execution time (similar to C/C++ profile capabilities)

Device "name"

Target device name.

Binary Container "name"

Binary container name.

Memory Data Transfers

For each DDR Bank, this shows the trace of all the read and write request transactions arriving at the bank from the host.

Kernel "name" 1:1:1

For each kernel and for each compute unit of that kernel, this section breaks down the activities originating from the compute unit.

Compute Unit: "name"

Compute unit name.

CU Stalls (%)

Stall signals are provided by the Vitis HLS tool to inform you when a portion of the circuit is stalling because of external memory accesses, internal streams (that is, dataflow), or external streams (that is, OpenCL pipes). The stall bus shown in detailed kernel trace compiles all of the lowest level stall signals and reports the percentage that are stalling at any point in time. This provides a factor of how much of the kernel is stalling at any point in the simulation.

For example, if there are 100 lowest level stall signals and 10 are active on a given clock cycle, then the CU Stall percentage is 10%. If one goes inactive, then it is 9%.

Data Transfers

This shows the read/write data transfer accesses originating from each Master AXI port of the compute unit to the DDR.

User Functions

This information is available for the HLS kernels and shows the user functions.

Function: "name"

Function name.

Dataflow/Pipeline Activity

This shows the number of parallel executions of the function if the function is implemented as a dataflow process.

Active Iterations

This shows the currently active iterations of the dataflow. The number of rows is dynamically incremented to accommodate the visualization of any concurrent execution.

StallNoContinue

This is a stall signal that tells if there were any output stalls experienced by the dataflow processes (function is done, but it has not received a continue from the adjacent dataflow process).

RTL Signals

These are the underlying RTL control signals that were used to interpret the above transaction view of the dataflow process.

Function Stalls

Shows the different types of stalls experienced by the process.

External Memory

Stalls experienced while accessing the DDR memory.

Internal-Kernel Pipe

If the compute units communicated between each other through pipes, then this shows the related stalls.

Intra-Kernel Dataflow

FIFO activity internal to the kernel.

Function I/O

Actual interface signals.

HLS FIFO

• This shows waveform for size of HLS FIFOs created inside non-RTL kernels
• The waveform is in Analog style
• It shows one entry for each kernel instance which has FIFO in it
• The analog waveform is produced by tracing on an internal HDL signal of the kernel which gives the current number of elements in the FIFO during simulation.

CU name

Name of the CU containing FIFO

FIFO instance name

Name of the FIFO instanc

mOutPtr["size:"0]

HDL signal which gives the number of elements currently in the FIFO during simulation