Managing Vivado Synthesis, Implementation, and Timing Closure - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-07-03
Version
2024.1 English
Tip: This topic requires an understanding of the Vivado Design Suite tools and design methodology as described in UltraFast Design Methodology Guide for FPGAs and SoCs (UG949), or the Versal Adaptive SoC Design Guide (UG1273).

As explained before, the Vitis linking process supports two different flows for implementing the linked hardware design: the Vitis Integrated Flow, and the Vitis Export to Vivado flow. Both of the flows use the Vivado Design Suite for synthesis and implementation of the linked system design. The way the Vivado tools are used is different between the two flows.

The Vitis Integrated Flow is shown in the following figure. An extensible hardware platform (.xsa) is built using the Vivado Design Suite and passed to the Vitis tool, where the platform is used for developing the AI Engine graph application and additional PL kernels for the system design. In the Vitis Integrated Flow, the system design is automatically synthesized and implemented in the Vivado Design Suite in the Vitis Integrated Flow during the v++ linking phase.

Figure 1. Vitis Integrated Flow

The Vitis Export to Vivado flow performs standard linking design modifications, but stops before running Vivado synthesis and instead encapsulates all relevant design data into a Vitis Metadata Archive (.vma) file to be imported back into the Vivado tools, as shown in the following figure. In this flow the .xsa file is passed to the Vitis design team for developing the AI Engine graph application and PL kernels for the system design, and the .vma file is returned to the Vivado tools, leaving simulation, synthesis and implementation to be manually completed by the user.

Figure 2. Vitis Export to Vivado Flow