RTL Configuration - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2024.1 English

The syn.rtl commands configure various attributes of the compiled RTL, the type of reset used, and the encoding of the state machines. It also allows you to use specific identification in the RTL. By default, these options are applied to the top-level design and all RTL blocks within the design.

Generate test vectors during hardware emulation in the Vitis tool flow when the kernel is synthesized as a Vitis kernel, to be used as a test bench for C/RTL Co-simulation in future design iterations.

Enables simulation or synthesis deadlock detection in the top-level RTL of an exported IP/XO file. The options are as follows:

  • none : Deadlock detection disabled
  • sim : Enables deadlock detection only for simulation/emulation. This is the default setting.
  • hw : Deadlock detection enabled in synthesized RTL IP. Adds ap_local_deadlock and ap_local_block signals to the IP to enable local and global deadlock detection.
Enable deadlock detection diagnosis for Vitis kernels (.xo) during hardware emulation of the Application.
Specify the 'fsm_encoding' RTL attribute value to guide RTL synthesis. The options are as follows:
  • auto:Allow the RTL Synthesis tool to determine the best state machine encoding
  • gray:Use gray state machine encoding
  • johnson:Use johnson state machine encoding
  • one_hot:Use one_hot state machine encoding
  • sequential:Use sequential state machine encoding
  • none:Disable state machine encoding, the state machine is synthesized exactly using the state code specified in the RTL (which is one_hot)
Specify the 'fsm_safe_state' RTL attribute value to guide RTL synthesis. This attribute can affect the quality of synthesis results, typically resulting in less performance with greater area. The options are as follows:
  • auto_safe_state:Implies Hamming-3 encoding.
  • default_state:Return the state machine to the default state.
  • power_on_state:Return the state machine to the POWER_ON state.
  • reset_state:Return the state machine to the RESET state.
  • none:Attribute not added to RTL, the state machine will not include safe state logic.
Specify a file whose contents will be inserted at the beginning of all generated RTL files. This allows you to ensure that the generated RTL files contain user specified content.
Add top level event and stall ports required by kernel profiling.
Important: This option relates to the v++ -c --profile.stall command, and must be manually added to the HLS component to ensure the stall profiling is available for use in the linked Application.
Specifies the top level function name as the prefix value for generated RTL modules. This option is ignored if syn.rtl.module_prefix is also specified. This is enabled by default.
Specify a prefix to be used for all generated RTL module names. Use this to override the defaul module prefix of the top-level function.
Enable keep attribute.
Use a register by default for all I/O signals.
Number of registers to add to reset signal.
Variables initialized in the C/C++ code are always initialized to the same value in the RTL and therefore in the bitstream. This initialization is performed only at power-on. It is not repeated when a reset is applied to the design.

The setting applied with the -reset option determines how registers and memories are reset.

  • none: No reset is added to the design.
  • control: Resets control registers, such as those used in state machines and those used to generate I/O protocol signals. This is the default setting.
  • state: Resets control registers and registers or memories derived from static or global variables in the C/C++ code. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
  • all: Resets all registers and memories in the design. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
Causes all registers to use an asynchronous reset. If this option is not specified a synchronous reset is used.
Defines the polarity of the reset signal to be either active-Low or active-High. The default setting is active-High.
Tip: The AXI protocol requires an active-Low reset. If your design uses AXI interfaces the tool will define this reset level with a warning if the syn.rtl.reset_level is active-High.