The use cases of AXI4 memory map I/O XO differs from AXI4-Stream I/O XO. AXI4 memory map XOs have few limitations on usage during the link stage of Vitis listed as below:
- Only AXI4 memory map Master I/O can be used.
- AXI4 memory map Master I/O can connect only with available slaves in the platform.
- AXI4 memory map Master I/O cannot communicate with kernel in the design.
For XO usage during link stage:
- To generate XO, developers can use the script available at $XILINX_VITIS/data/emulation/XO/scripts/aximm_xo_creation.sh
- Required configuration of XO can be generated using the above
script.
$XILINX_VITIS/data/emulation/XO/scripts/aximm_xo_creation.sh --address_width <adr_width> --data_width <data_width> --id_width <id_width> --output_path <output_path>.xo $XILINX_VITIS/data/emulation/XO/scripts/aximm_xo_creation.sh --address_width 64 --data_width 64 --id_width 4 --output_path sim_ipc_aximm_master.xo - After generating XO, it can be used in the design with
configuration as shown below (sample usage, actual connection to be done based on
the
requirement):
[connectivity] nk=sim_ipc_aximm_master:1:aximm_master sp=aximm_master.M_AXIMM:HBM[0]