PL Kernel Properties - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

In the Vitis development flow, PL kernels as compiled object files (.xo) are the processing elements executing in the programmable logic region of the AMD device. The Vitis core development kit supports PL kernels written in C/C++ compiled by the v++ HLS compiler, and RTL IP packaged in the Vivado Design Suite.

Regardless of source language, all PL kernels have the same properties and must adhere to same set of requirements.

  • Control Scheme: Kernels can be defined as software controllable, or data-driven. This means that the PL kernel is controlled through a software application running XRT or using available drivers, or is not managed by software and is instead driven by the arrival of data.
  • HW Interfaces: Kernels must use AXI4 interfaces in the design regardless of whether software controlled or data driven.
  • Clocks and Resets: Kernels must have clocks to sync kernels and platforms into a system, and optional resets for additional control.