Package Parameter Guidelines

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)

Document ID
DS925
Release Date
2023-12-26
Revision
1.26 English

The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows.

Table 1. Package Skew
Symbol Description Device Package Value Units
PKGSKEW Package Skew 1, 2 XCZU1 SBVA484 190 ps
SFVA625 86 ps
SFVC784 115 ps
UBVA494 56 ps
XCZU2 SBVA484 105 ps
SFVA625 108 ps
SFVC784 93 ps
UBVA530 78 ps
XCZU3 SBVA484 105 ps
SFVA625 108 ps
SFVC784 93 ps
UBVA530 78 ps
XCZU3T SFVC784 70 ps
SFVD784 93 ps
XCZU4 SFVC784 133 ps
FBVB900 159 ps
XCZU5 SFVC784 133 ps
FBVB900 159 ps
XCZU6 FFVC900 119 ps
FFVB1156 134 ps
XCZU7 FBVB900 141 ps
FFVC1156 175 ps
FFVF1517 305 ps
XCZU9 FFVC900 119 ps
FFVB1156 134 ps
XCZU11 FFVC1156 170 ps
FFVB1517 176 ps
FFVF1517 186 ps
FFVC1760 215 ps
XCZU15 FFVC900 118 ps
FFVB1156 132 ps
XCZU17 FFVB1517 221 ps
FFVC1760 226 ps
FFVD1760 178 ps
FFVE1924 174 ps
XCZU19 FFVB1517 221 ps
FFVC1760 226 ps
FFVD1760 178 ps
FFVE1924 174 ps
PKGSKEW Package Skew 1, 2 XAZU1EG SBVA484 190 ps
SFVA625 86 ps
SFVC784 115 ps
XAZU2EG SBVA484 105 ps
SFVA625 108 ps
SFVC784 93 ps
XAZU3EG SBVA484 105 ps
SFVA625 108 ps
SFVC784 93 ps
XAZU3TEG SFVC784 70 ps
SFVD784 93 ps
XAZU4EV SFVC784 133 ps
XAZU5EV SFVC784 133 ps
XAZU7EV FBVB900 141 ps
XAZU11EG FFVF1517 186 ps
XQZU3EG SFRA484 106 ps
SFRC784 93 ps
XQZU5EV SFRC784 133 ps
FFRB900 155 ps
XQZU7EV FFRB900 141 ps
FFRC1156 176 ps
XQZU9EG FFRC900 119 ps
FFRB1156 135 ps
XQZU11EG FFRC1156 170 ps
FFRC1760 214 ps
XQZU15EG FFRC900 119 ps
FFRB1156 127 ps
XQZU19EG FFRB1517 211 ps
FFRC1760 228 ps
  1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball.
  2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.