PS eMMC Standard Interface

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)

Document ID

DS925

Release Date

2024-07-12

Revision

1.27 English

Table 1. eMMC Standard Interface
Symbol	Description¹	Min	Max	Units
eMMC Standard Interface
T_DCEMMCHSCLK	eMMC clock duty cycle	45	55	%
T_EMMCHSCKO	Clock to output delay, all outputs	–2.0	4.5	ns
T_EMMCHSDCK	Input setup time, all inputs	2.0	–	ns
T_EMMCHSCKD	Input hold time, all inputs	2.0	–	ns
F_EMMCHSCLK	eMMC clock frequency	–	25	MHz
eMMC High-Speed SDR Interface
T_DCEMMCHSCLK	eMMC high-speed SDR clock duty cycle	45	55	%
T_EMMCHSCKO	Clock to output delay, all outputs²	3.2	16.8	ns
T_EMMCHSDIVW	Input valid data window³	0.4	–	UI
F_EMMCHSCLK	eMMC high speed SDR clock frequency	–	50	MHz
eMMC High-Speed DDR Interface
T_DCEMMCDDRCLK	eMMC high-speed DDR clock duty cycle	45	55	%
T_EMMCDDRSCKO1	Data clock to output delay²	2.7	7.3	ns
T_EMMCDDRIVW	Input valid data window³	3.5	–	ns
T_EMMCDDRSCKO2	Command clock to output delay	3.2	16	ns
T_EMMCDDRDCK2	Command input setup time	3.9	–	ns
T_EMMCDDRCKD2	Command input hold time	2.5	–	ns
F_EMMCDDRCLK	eMMC high-speed DDR clock frequency	–	50	MHz
eMMC HS200 Interface
T_{DCEMMCHS200CLK}	eMMC HS200 clock duty cycle	40	60	%
T_EMMCHS200CKO	Clock to output delay, all outputs²	1.0	3.4	ns
T_EMMCSDR1IVW	Input valid data window³	0.4	–	UI
F_EMMCHS200CLK	eMMC HS200 clock frequency	–	200	MHz
The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load. For eMMC high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other eMMC modes, the test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load. This specification is achieved using pre-determined DLL tuning. This specification is required for capturing input data using DLL tuning.