More information and documentation on solutions using the integrated
100 Gb/s Ethernet block can be found at
UltraScale+ Integrated 100G
Ethernet MAC/PCS
. The
UltraScale
Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each
Zynq UltraScale+ MPSoC.
| Symbol | Description | Speed Grade and VCCINT Operating Voltages | Units | ||||
|---|---|---|---|---|---|---|---|
| 0.90V | 0.85V | 0.72V | |||||
| -3 | -2 | -1 | -2 | -1 | |||
| CAUI-10 Mode | |||||||
| FTX_CLK | Transmit clock | 390.625 | 390.625 | 322.266 | 322.266 | 322.266 | MHz |
| FRX_CLK | Receive clock | 390.625 | 390.625 | 322.266 | 322.266 | 322.266 | MHz |
| FRX_SERDES_CLK | Receive serializer/deserializer clock | 390.625 | 390.625 | 322.266 | 322.266 | 322.266 | MHz |
| FDRP_CLK | Dynamic reconfiguration port clock | 250.00 | 250.00 | 250.00 | 250.00 | 250.00 | MHz |
| CAUI-4, CAUI-4 + RS-FEC, and RS-FEC Transcode Bypass Modes | |||||||
| FTX_CLK | Transmit clock | 390.625 | 322.266 | 322.266 | 322.266 | N/A | MHz |
| FRX_CLK | Receive clock | 390.625 | 322.266 | 322.266 | 322.266 | N/A | MHz |
| FRX_SERDES_CLK | Receive serializer/deserializer clock | 390.625 | 322.266 | 322.266 | 322.266 | N/A | MHz |
| FDRP_CLK | Dynamic reconfiguration port clock | 250.00 | 250.00 | 250.00 | 250.00 | N/A | MHz |