Input Delay Measurement Methodology

The following table shows the test setup parameters used for measuring input delay.

Table 1. Input Delay Measurement Methodology
Description	I/O Standard Attribute	V_L ^{1, 2}	V_H ^{1, 2}	V_MEAS ^{1, 4}	V_REF ^{1, 3, 5}
LVCMOS, 1.2V	LVCMOS12	0.1	1.1	0.6	–
LVCMOS, LVDCI, HSLVDCI, 1.5V	LVCMOS15, LVDCI_15, HSLVDCI_15	0.1	1.4	0.75	–
LVCMOS, LVDCI, HSLVDCI, 1.8V	LVCMOS18, LVDCI_18, HSLVDCI_18	0.1	1.7	0.9	–
LVCMOS, 2.5V	LVCMOS25	0.1	2.4	1.25	–
LVCMOS, 3.3V	LVCMOS33	0.1	3.2	1.65	–
LVTTL, 3.3V	LVTTL	0.1	3.2	1.65	–
HSTL (high-speed transceiver logic), class I, 1.2V	HSTL_I_12	V_REF – 0.25	V_REF + 0.25	V_REF	0.6
HSTL, class I, 1.5V	HSTL_I	V_REF – 0.325	V_REF + 0.325	V_REF	0.75
HSTL, class I, 1.8V	HSTL_I_18	V_REF – 0.4	V_REF + 0.4	V_REF	0.9
HSUL (high-speed unterminated logic), 1.2V	HSUL_12	V_REF – 0.25	V_REF + 0.25	V_REF	0.6
SSTL12 (stub series terminated logic), 1.2V	SSTL12	V_REF – 0.25	V_REF + 0.25	V_REF	0.6
SSTL135 and SSTL135 class II, 1.35V	SSTL135, SSTL135_II	V_REF – 0.2875	V_REF + 0.2875	V_REF	0.675
SSTL15 and SSTL15 class II, 1.5V	SSTL15, SSTL15_II	V_REF – 0.325	V_REF + 0.325	V_REF	0.75
SSTL18, class I and II, 1.8V	SSTL18_I, SSTL18_II	V_REF – 0.4	V_REF + 0.4	V_REF	0.9
POD10, 1.0V	POD10	V_REF – 0.2	V_REF + 0.2	V_REF	0.7
POD12, 1.2V	POD12	V_REF – 0.24	V_REF + 0.24	V_REF	0.84
DIFF_HSTL, class I, 1.2V	DIFF_HSTL_I_12	0.6 – 0.25	0.6 + 0.25	0⁶	–
DIFF_HSTL, class I, 1.5V	DIFF_HSTL_I	0.75 – 0.325	0.75 + 0.325	0⁶	–
DIFF_HSTL, class I, 1.8V	DIFF_HSTL_I_18	0.9 – 0.4	0.9 + 0.4	0⁶	–
DIFF_HSUL, 1.2V	DIFF_HSUL_12	0.6 – 0.25	0.6 + 0.25	0⁶	–
DIFF_SSTL, 1.2V	DIFF_SSTL12	0.6 – 0.25	0.6 + 0.25	0⁶	–
DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V	DIFF_SSTL135, DIFF_SSTL135_II	0.675 – 0.2875	0.675 + 0.2875	0⁶	–
DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V	DIFF_SSTL15, DIFF_SSTL15_II	0.75 – 0.325	0.75 + 0.325	0⁶	–
DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V	DIFF_SSTL18_I, DIFF_SSTL18_II	0.9 – 0.4	0.9 + 0.4	0⁶	–
DIFF_POD10, 1.0V	DIFF_POD10	0.5 – 0.2	0.5 + 0.2	0⁶	–
DIFF_POD12, 1.2V	DIFF_POD12	0.6 – 0.25	0.6 + 0.25	0⁶	–
LVDS (low-voltage differential signaling), 1.8V	LVDS	0.9 – 0.125	0.9 + 0.125	0⁶	–
LVDS_25, 2.5V	LVDS_25	1.25 – 0.125	1.25 + 0.125	0⁶	–
SUB_LVDS, 1.8V	SUB_LVDS	0.9 – 0.125	0.9 + 0.125	0⁶	–
SLVS, 1.8V	SLVS_400_18	0.9 – 0.125	0.9 + 0.125	0⁶	–
SLVS, 2.5V	SLVS_400_25	1.25 – 0.125	1.25 + 0.125	0⁶	–
LVPECL, 2.5V	LVPECL	1.25 – 0.125	1.25 + 0.125	0⁶	–
MIPI D-PHY (high speed) 1.2V	MIPI_DPHY_DCI_HS	0.2 – 0.125	0.2 + 0.125	0⁶	–
MIPI D-PHY (low power) 1.2V	MIPI_DPHY_DCI_LP	0.715 – 0.2	0.715 + 0.2	0⁶	–
The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. Input waveform switches between V_L and V_H. Measurements are made at typical, minimum, and maximum V_REF values. Reported delays reflect worst case of these measurements. V_REF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the V_REF/V_MEAS parameters found in IBIS models and/or noted in Figure 1. The value given is the differential input voltage.