PS Quad-SPI Controller Interface

Table 1. Generic Quad-SPI Interface
Symbol	Description¹	Load Conditions²	Min	Max	Units
Quad-SPI device clock frequency operating at 150 MHz. Loopback enabled.³ LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
T_DCQSPICLK1	Quad-SPI clock duty cycle	15 pF	45	55	%
T_QSPISSSCLK1	Slave select asserted to next clock edge	15 pF	5.0	–	ns
T_QSPISCLKSS1	Clock edge to slave select deasserted	15 pF	5.0	–	ns
T_QSPICKO1	Clock to output delay, all outputs	15 pF	2.9	4.5	ns
T_QSPIDCK1	Setup time, all inputs	15 pF	0.9	–	ns
T_QSPICKD1	Hold time, all inputs	15 pF	1.0	–	ns
F_QSPICLK1	Quad-SPI device clock frequency	15 pF	–	150	MHz
F_QSPIREFCLK1	Quad-SPI reference clock frequency	15 pF	–	300	MHz
Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled.³ LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
T_DCQSPICLK2	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK2	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK2	Slave select asserted to next clock edge	15 pF	5.0	–	ns
T_QSPISSSCLK2	Slave select asserted to next clock edge	30 pF	5.0	–	ns
T_QSPISCLKSS2	Clock edge to slave select deasserted	15 pF	5.0	–	ns
T_QSPISCLKSS2	Clock edge to slave select deasserted	30 pF	5.0	–	ns
T_QSPICKO2	Clock to output delay, all outputs	15 pF	3.2	7.4	ns
T_QSPICKO2	Clock to output delay, all outputs	30 pF	3.2	7.4	ns
T_QSPIDCK2	Setup time, all inputs	15 pF	2.3	–	ns
T_QSPIDCK2	Setup time, all inputs	30 pF	2.3	–	ns
T_QSPICKD2	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD2	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPICLK2	Quad-SPI device clock frequency	15 pF	–	100	MHz
F_QSPICLK2	Quad-SPI device clock frequency	30 pF	–	100	MHz
F_QSPIREFCLK2	Quad-SPI reference clock frequency	15 pF	–	200	MHz
F_QSPIREFCLK2	Quad-SPI reference clock frequency	30 pF	–	200	MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.
T_DCQSPICLK3	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK3	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK3	Slave select asserted to next clock edge⁴	15 pF	7.0	–	ns
T_QSPISSSCLK3	Slave select asserted to next clock edge⁴	30 pF	7.0	–	ns
T_QSPISCLKSS3	Clock edge to slave select deasserted	15 pF	7.0	–	ns
T_QSPISCLKSS3	Clock edge to slave select deasserted	30 pF	7.0	–	ns
T_QSPICKO3	Clock to output delay, all outputs	15 pF	5.2	14.8	ns
T_QSPICKO3	Clock to output delay, all outputs	30 pF	5.2	14.8	ns
T_QSPIDCK3	Setup time, all inputs	15 pF	13.4	–	ns
T_QSPIDCK3	Setup time, all inputs	30 pF	14.1	–	ns
T_QSPICKD3	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD3	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPIREFCLK3	Quad-SPI reference clock frequency	15 pF	–	160	MHz
F_QSPIREFCLK3	Quad-SPI reference clock frequency	30 pF	–	160	MHz
F_QSPICLK3	Quad-SPI clock frequency	15 pF	–	40	MHz
F_QSPICLK3	Quad-SPI clock frequency	30 pF	–	40	MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.
T_DCQSPICLK4	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK4	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK4	Slave select asserted to next clock edge⁴	15 pF	7.0	–	ns
T_QSPISSSCLK4	Slave select asserted to next clock edge⁴	30 pF	7.0	–	ns
T_QSPISCLKSS4	Clock edge to slave select deasserted	15 pF	7.0	–	ns
T_QSPISCLKSS4	Clock edge to slave select deasserted	30 pF	7.0	–	ns
T_QSPICKO4	Clock to output delay, all outputs	15 pF	5.2	14.8	ns
T_QSPICKO4	Clock to output delay, all outputs	30 pF	5.2	14.8	ns
T_QSPIDCK4	Setup time, all inputs	15 pF	13.9	–	ns
T_QSPIDCK4	Setup time, all inputs	30 pF	14.9	–	ns
T_QSPICKD4	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD4	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPIREFCLK4	Quad-SPI reference clock frequency	15 pF	–	160	MHz
F_QSPIREFCLK4	Quad-SPI reference clock frequency	30 pF	–	160	MHz
F_QSPICLK4	Quad-SPI clock frequency	15 pF	–	40	MHz
F_QSPICLK4	Quad-SPI clock frequency	30 pF	–	40	MHz
The test conditions are configured for the generic Quad-SPI interface at 150/100 MHz with a 12 mA drive strength and fast slew rate. 30 pF loads are for dual-parallel stacked or stacked modes. When the Quad-SPI clock frequency is greater than 40 MHz, the Quad-SPI feedback clock (MIO[6]) must be enabled in the processing system configuration wizard (PCW), and the associated MIO[6] (clk_for_lpbk) pin must be left unconnected on the board. T_QSPISSSCLK3 and T_QSPISSSCLK4 are only valid when two reference clock cycles are programmed between the chip select and clock.

Table 2. Linear Quad-SPI Interface
Symbol	Description¹	Load Conditions²	Min	Max	Units
Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled.³ LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
T_DCQSPICLK5	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK5	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK5	Slave select asserted to next clock edge⁴	15 pF	5.0	–	ns
T_QSPISSSCLK5	Slave select asserted to next clock edge⁴	30 pF	5.0	–	ns
T_QSPISCLKSS5	Clock edge to slave select deasserted	15 pF	5.0	–	ns
T_QSPISCLKSS5	Clock edge to slave select deasserted	30 pF	5.0	–	ns
T_QSPICKO5	Clock to output delay, all outputs	15 pF	3.2	7.4	ns
T_QSPICKO5	Clock to output delay, all outputs	30 pF	3.2	7.4	ns
T_QSPIDCK5	Setup time, all inputs	15 pF	2.4	–	ns
T_QSPIDCK5	Setup time, all inputs	30 pF	2.4	–	ns
T_QSPICKD5	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD5	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPIREFCLK5	Quad-SPI reference clock frequency	15 pF	–	200	MHz
F_QSPIREFCLK5	Quad-SPI reference clock frequency	30 pF	–	200	MHz
F_QSPICLK5	Quad-SPI device clock frequency	15 pF	–	100	MHz
F_QSPICLK5	Quad-SPI device clock frequency	30 pF	–	100	MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.
T_DCQSPICLK6	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK6	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK6	Slave select asserted to next clock edge	15 pF	7.0	–	ns
T_QSPISSSCLK6	Slave select asserted to next clock edge	30 pF	7.0	–	ns
T_QSPISCLKSS6	Clock edge to slave select deasserted	15 pF	7.0	–	ns
T_QSPISCLKSS6	Clock edge to slave select deasserted	30 pF	7.0	–	ns
T_QSPICKO6	Clock to output delay, all outputs	15 pF	5.2	14.8	ns
T_QSPICKO6	Clock to output delay, all outputs	30 pF	5.2	14.8	ns
T_QSPIDCK6	Setup time, all inputs	15 pF	13.4	–	ns
T_QSPIDCK6	Setup time, all inputs	30 pF	13.4	–	ns
T_QSPICKD6	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD6	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPIREFCLK6	Quad-SPI reference clock frequency	15 pF	–	160	MHz
F_QSPIREFCLK6	Quad-SPI reference clock frequency	30 pF	–	160	MHz
F_QSPICLK6	Quad-SPI device clock frequency	15 pF	–	40	MHz
F_QSPICLK6	Quad-SPI device clock frequency	30 pF	–	40	MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.
T_DCQSPICLK7	Quad-SPI clock duty cycle	15 pF	45	55	%
T_DCQSPICLK7	Quad-SPI clock duty cycle	30 pF	45	55	%
T_QSPISSSCLK7	Slave select asserted to next clock edge	15 pF	7.0	–	ns
T_QSPISSSCLK7	Slave select asserted to next clock edge	30 pF	7.0	–	ns
T_QSPISCLKSS7	Clock edge to slave select deasserted	15 pF	7.0	–	ns
T_QSPISCLKSS7	Clock edge to slave select deasserted	30 pF	7.0	–	ns
T_QSPICKO7	Clock to output delay, all outputs	15 pF	5.2	14.8	ns
T_QSPICKO7	Clock to output delay, all outputs	30 pF	5.2	14.8	ns
T_QSPIDCK7	Setup time, all inputs	15 pF	14.0	–	ns
T_QSPIDCK7	Setup time, all inputs	30 pF	14.0	–	ns
T_QSPICKD7	Hold time, all inputs	15 pF	0.0	–	ns
T_QSPICKD7	Hold time, all inputs	30 pF	0.0	–	ns
F_QSPIREFCLK7	Quad-SPI reference clock frequency	15 pF	–	160	MHz
F_QSPIREFCLK7	Quad-SPI reference clock frequency	30 pF	–	160	MHz
F_QSPICLK7	Quad-SPI device clock frequency	15 pF	–	40	MHz
F_QSPICLK7	Quad-SPI device clock frequency	30 pF	–	40	MHz
The test conditions are configured for the linear Quad-SPI interface at 100 MHz with a 12 mA drive strength and fast slew rate. 30 pF loads are for stacked modes. When the Quad-SPI clock frequency is greater than 40 MHz, the Quad-SPI feedback clock (MIO[6]) must be enabled in the processing system configuration wizard (PCW), and the associated MIO[6] (clk_for_lpbk) pin must be left unconnected on the board. T_QSPISSSCLK5 is only valid when two reference clock cycles are programmed between chip select and clock.