Clock Buffers and Networks

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2024-07-12
Revision
1.27 English
Table 1. Clock Buffers Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Global Clock Switching Characteristics (Including BUFGCTRL)
FMAX Maximum frequency of a global clock tree (BUFG) 891 775 667 725 667 MHz
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)
FMAX Maximum frequency of a global clock buffer with input divide capability (BUFGCE_DIV) 891 775 667 725 667 MHz
Global Clock Buffer with Clock Enable (BUFGCE)
FMAX Maximum frequency of a global clock buffer with clock enable (BUFGCE) 891 775 667 725 667 MHz
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)
FMAX Maximum frequency of a leaf clock buffer with clock enable (BUFCE_LEAF) 891 775 667 725 667 MHz
GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
FMAX Maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 512 512 512 512 512 MHz