PS SD/SDIO Controller Interface

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2024-07-12
Revision
1.27 English
Table 1. SD/SDIO Interface
Symbol Description 1 Min Max Units
SD/SDIO Interface DDR50 Mode
TDCDDRCLK SD device clock duty cycle 45 55 %
TSDDDRCKO1 Clock to output delay, data 2 1.0 6.8 ns
TSDDDRIVW Input valid data window 3 3.5 – ns
TSDDDRDCK2 Input setup time, command 4.7 – ns
TSDDDRCKD2 Input hold time, command 1.5 – ns
TSDDDRCKO2 Clock to output delay, command 1.0 13.8 ns
FSDDDRCLK High-speed mode SD device clock frequency – 50 MHz
SD/SDIO Interface SDR104

TDCSDHSCLK1

SD device clock duty cycle 40 60 %
TSDSDRCKO1 Clock to output delay, all output 2 1.0 3.2 ns
TSDSDR1IVW Input valid data window 3 0.5 – UI
FSDSDRCLK1 SDR104 mode device clock frequency – 200 MHz
SD/SDIO Interface SDR50/25

TDCSDHSCLK2

SD device clock duty cycle 40 60 %
TSDSDRCKO2 Clock to output delay, all outputs 2 1.0 6.8 ns
TSDSDR2IVW Input valid data window 3 0.3 – UI
FSDSDRCLK2 SDR50 mode device clock frequency – 100 MHz
SDR25 mode device clock frequency – 50 MHz
SD/SDIO Interface SDR12

TDCSDHSCLK3

SD device clock duty cycle 40 60 %
TSDSDRCKO3 Clock to output delay, all outputs 1.0 36.8 ns
TSDSDRDCK3 Input setup time, all inputs 10.0 – ns
TSDSDRCKD3 Input hold time, all inputs 1.5 – ns
FSDSDRCLK3 SDR12 mode device clock frequency – 25 MHz
SD/SDIO Interface High-Speed Mode
TDCSDHSCLK SD device clock duty cycle 47 53 %
TSDHSCKO Clock to output delay, all outputs 2 2.2 13.8 ns
TSDHSDIVW Input valid data window 3 0.35 – UI
FSDHSCLK High-speed mode SD device clock frequency – 50 MHz
SD/SDIO Interface Standard Mode
TDCSDSCLK SD device clock duty cycle 45 55 %
TSDSCKO Clock to output delay, all outputs –2.0 4.5 ns
TSDSDCK Input setup time, all inputs 2.0 – ns
TSDSCKD Input hold time, all inputs 2.0 – ns
FSDIDCLK Clock frequency in identification mode – 400 KHz
FSDSCLK Standard SD device clock frequency – 19 MHz
  1. The test conditions SD/SDIO standard mode (default speed mode) use an 8 mA drive strength, fast slew rate, and a 30 pF load. For SD/SDIO high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other SD/SDIO modes, the test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load.
  2. This specification is achieved using pre-determined DLL tuning.
  3. This specification is required for capturing input data using DLL tuning.