Programmable Logic (PL) Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in the Zynq UltraScale+ MPSoCs. These values are subject to the same guidelines as the AC Switching Characteristics section.

In each of the following LVDS performance tables, the I/O bank type is either high performance (HP) or high density (HD).

In LVDS component mode:

For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades.
For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.

Table 1. LVDS Component Mode Performance
Description	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages										Units
		0.90V		0.85V				0.72V
		-3		-2		-1		-2		-1
		Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
LVDS TX DDR (OSERDES 4:1, 8:1)	HP	0	1250	0	1250	0	1250	0	1250	0	1250	Mb/s
LVDS TX SDR (OSERDES 2:1, 4:1)	HP	0	625	0	625	0	625	0	625	0	625	Mb/s
LVDS RX DDR (ISERDES 1:4, 1:8)¹	HP	0	1250	0	1250	0	1250	0	1250	0	1250	Mb/s
LVDS RX DDR	HD	0	250	0	250	0	250	0	250	0	250	Mb/s
LVDS RX SDR (ISERDES 1:2, 1:4)¹	HP	0	625	0	625	0	625	0	625	0	625	Mb/s
LVDS RX SDR	HD	0	125	0	125	0	125	0	125	0	125	Mb/s
LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.

Table 2. LVDS Native Mode Performance
Description^{1, 2}	DATA_WIDTH	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages										Units
			0.90V		0.85V				0.72V
			-3³		-2³		-1³		-2³		-1³
			Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
LVDS TX DDR (TX_BITSLICE)	4	HP	375	1600	375	1600	375	1600	375	1400	375	1260	Mb/s
LVDS TX DDR (TX_BITSLICE)	8	HP	375	1600	375	1600	375	1600	375	1600	375	1600	Mb/s
LVDS TX SDR (TX_BITSLICE)	4	HP	187.5	800	187.5	800	187.5	800	187.5	700	187.5	630	Mb/s
LVDS TX SDR (TX_BITSLICE)	8	HP	187.5	800	187.5	800	187.5	800	187.5	800	187.5	800	Mb/s
LVDS RX DDR (RX_BITSLICE)⁴	4	HP	375	1600⁵	375	1600⁵	375	1600⁵	375	1400⁵	375	1260⁵	Mb/s
LVDS RX DDR (RX_BITSLICE)⁴	8	HP	375	1600⁵	375	1600⁵	375	1600⁵	375	1600⁵	375	1600⁵	Mb/s
LVDS RX SDR (RX_BITSLICE)⁴	4	HP	187.5	800	187.5	800	187.5	800	187.5	700	187.5	630	Mb/s
LVDS RX SDR (RX_BITSLICE)⁴	8	HP	187.5	800	187.5	800	187.5	800	187.5	800	187.5	800	Mb/s
Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_F_VCOMIN/2. In the SBVA484, SFRA484, UBVA494, and UBVA530 packages, the maximum data rate is 1260 Mb/s for DDR interfaces and 630 Mb/s for SDR interfaces. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing. Asynchronous receiver performance is limited to 1300 Mb/s for -3/-2 speed grades and to 1250 Mb/s for -1 speed grades.

Table 3. MIPI D-PHY Performance
Description	I/O Bank Type	Conditions¹	Speed Grade and V_CCINT Operating Voltages					Units
			0.90V	0.85V		0.72V
			-3	-2	-1	-2	-1
Maximum MIPI D-PHY transmitter or receiver data rate per lane	HP	XC and XA devices using Vivado tools 2019.2.2 or later	2500	2500	2500²	2500	1260	Mb/s
		XC and XA devices using Vivado tools 2019.1.1 through 2019.2.1	2500	2500	1260	2500	1260	Mb/s
		XC and XA devices using Vivado tools 2019.1 or earlier	1500	1500	1260	1260	1260	Mb/s
		XQ devices	1500	1500	1260	1260	1260	Mb/s
		All devices in SBVA484, SFRA484, UBVA494, and UBVA530 packages	1260	1260	1260	1260	1260	Mb/s
For applicable conditions, the lower maximum data rate applies. XA devices with the -1Q speed grade require Vivado tools 2020.1, or later, for data rates greater than 1260 Mb/s.

Table 4. LVDS Native-Mode 1000BASE-X Support
Description¹	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages
		0.90V	0.85V		0.72V
		-3	-2	-1	-2	-1
1000BASE-X	HP	Yes
1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

The following table provides the maximum data rates for applicable memory standards using the Zynq UltraScale+ MPSoC memory PHY. Refer to Memory Solutions for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale Architecture PCB Design User Guide (UG583), electrical analysis, and characterization of the system.

Table 5. Maximum Physical Interface (PHY) Rate for Memory Interfaces
Memory Standard	Packages¹	DRAM Type	Speed Grade and V_CCINT Operating Voltages					Units
			0.90V	0.85V		0.72V
			-3	-2	-1	-2	-1
DDR4	All FFV, FFR, and FBVB900 packages	Single rank component	2666	2666	2400	2400	2133	Mb/s
		1 rank DIMM^{2, 3, 4}	2400	2400	2133	2133	1866	Mb/s
		2 rank DIMM^{2, 5}	2133	2133	1866	1866	1600	Mb/s
		4 rank DIMM^{2, 6}	1600	1600	1333	1333	N/A	Mb/s
	SFVC784, SFRC784, SFVD784, and SFVE784	Single rank component	2400	2400	2133	2133	1866	Mb/s
		1 rank DIMM^{2, 3}	2133	2133	1866	1866	1600	Mb/s
		2 rank DIMM^{2, 5}	1866	1866	1600	1600	1600	Mb/s
DDR3	All FFV, FFR, and FBVB900 packages	Single rank component	2133	2133	2133	2133	1866	Mb/s
		1 rank DIMM^{2, 3}	1866	1866	1866	1866	1600	Mb/s
		2 rank DIMM^{2, 5}	1600	1600	1600	1600	1333	Mb/s
		4 rank DIMM^{2, 6}	1066	1066	1066	1066	800	Mb/s
	SFVC784, SFRC784, SFVD784, and SFVE784	Single rank component	1866	1866	1866	1866	1600	Mb/s
		1 rank DIMM^{2, 3}	1600	1600	1600	1600	1600	Mb/s
		2 rank DIMM^{2, 5}	1600	1600	1600	1600	1333	Mb/s
		4 rank DIMM^{2, 6}	1066	1066	1066	1066	800	Mb/s
DDR3L	All FFV, FFR, and FBVB900 packages	Single rank component	1866	1866	1866	1866	1600	Mb/s
		1 rank DIMM^{2, 3}	1600	1600	1600	1600	1333	Mb/s
		2 rank DIMM^{2, 5}	1333	1333	1333	1333	1066	Mb/s
		4 rank DIMM^{2, 6}	800	800	800	800	606	Mb/s
	SFVC784, SFRC784, SFVD784, and SFVE784	Single rank component	1600	1600	1600	1600	1600	Mb/s
		1 rank DIMM^{2, 3}	1600	1600	1600	1600	1333	Mb/s
		2 rank DIMM^{2, 5}	1333	1333	1333	1333	1066	Mb/s
		4 rank DIMM^{2, 6}	800	800	800	800	606	Mb/s
QDR II+	All	Single rank component⁷	633	633	600	600	550	MHz
RLDRAM 3	All FFV, FFR, and FBVB900 packages	Single rank component	1200	1200	1066	1066	933	MHz
RLDRAM 3	SFVC784, SFRC784, SFVD784, and SFVE784	Single rank component	1066	1066	933	933	800	MHz
QDR IV XP	All	Single rank component	1066	1066	1066	933	933	MHz
LPDDR3	All	Single rank component	1600	1600	1600	1600	1600	Mb/s
The SBVA484, SFRA484, SFVA625, UBVA494, and UBVA530 packages do not support the PL memory interfaces. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot. For the DDR4 DDP components at -3 and -2 (V_CCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (V_CCINT = 0.85V) speed grades. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot. Includes: 2 rank 2 slot, 4 rank 1 slot. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.