UltraRAM Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2024-07-12
Revision
1.27 English

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoCs that include this memory.

Table 1. UltraRAM Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Maximum Frequency
FMAX UltraRAM maximum frequency with OREG_B = True 650 600 575 500 481 MHz
FMAX_ECC_NOPIPELINE UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = True 435 400 386 312 303 MHz
FMAX_NOPIPELINE UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = False 528 500 478 404 389 MHz
TPW 1 Minimum pulse width 650 700 730 800 832 ps
TRSTPW Asynchronous reset minimum pulse width. One cycle required 1 clock cycle
  1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.