PS Clocks

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)

Document ID: DS925
Release Date: 2024-07-12
Revision: 1.27 English

Table 1. PS Reference Clock Requirements
Symbol	Description¹	Min	Typ	Max	Units
T_RMSJPSCLK	PS_REF_CLK input RMS clock jitter	–	–	3	ps
T_PJPSCLK	PS_REF_CLK input period jitter (peak-to-peak) Number of clock cycles = 10,000	–	–	50	ps
T_DCPSCLK	PS_REF_CLK duty cycle	45	–	55	%
T_RFPSCLK	PS_REF_CLK rise time (20%–80%) and fall time (80%–20%)	–	–	2.22	ns
F_PSCLK	PS_REF_CLK frequency	27	–	60	MHz
The values in this table are applicable to alternative PS reference clock inputs ALT_REF_CLK, AUX_REF_CLK, and VIDEO_CLK.

Table 2. PS RTC Crystal Requirements
Symbol	Description¹	Min	Typ	Max	Units
F_XTAL	Parallel resonance crystal frequency	–	32.8	–	KHz
T_FTXTAL	Frequency tolerance	–20	–	20	ppm
C_XTAL	Load capacitance for crystal parallel resonance	–	12.5	–	pF
R_ESR	Crystal ESR (16.8 and 19.2 MHz)	–	70	–	KΩ
C_SHUNT	Crystal shunt capacitance	–	1.4	–	pF
See the crystal circuit example in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

Table 3. PS PLL Switching Characteristics
Symbol	Description	Speed Grade			Units
Symbol	Description	-3	-2	-1	Units
T_LOCKPSPLL	PLL maximum lock time	100	100	100	µs
F_PSPLLMAX	PLL maximum output frequency	1600	1600	1600	MHz
F_PSPLLMIN	PLL minimum output frequency	750	750	750	MHz
F_PSPLLVCOMAX	PLL maximum VCO frequency	3000	3000	3000	MHz
F_PSPLLVCOMIN	PLL minimum VCO frequency	1500	1500	1500	MHz

Table 4. PS Reset Assertion Timing Requirements
Symbol	Description	Min	Typ	Max	Units
T_PSPOR	Required PS_POR_B assertion time¹	10	–	–	µs
T_PSRST	Required PS_SRST_B assertion time	3	–	–	PS_REF_CLK Clock Cycles
PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of T_PSPOR after all the PS supply voltages reach minimum levels. PS_POR_B must be asserted Low for the duration of T_POR,MAX when the PS and PL power-up at the same time and the application uses both the PS and PL after power-up.

Table 5. PS Clocks Switching Characteristics
Symbol	Description	Speed Grade			Units
Symbol	Description	-3	-2	-1	Units
F_{TOPSW_MAINMAX}	FPD AXI interconnect clock maximum frequency	600	533	533	MHz
F_{TOPSW_LSBUSMAX}	FPD APB bus clock maximum frequency	100	100	100	MHz
F_GDMAMAX	FPD-DMA controller clock maximum frequency	600	600	600	MHz
F_DPDMAMAX	DisplayPort controller clock maximum frequency	600	600	600	MHz
F_{LPD_SWITCH_CTRLMAX}	LPD AXI interconnect clock maximum frequency	600	500	500	MHz
F_{LPD_LSBUS_CTRLMAX}	LPD APB bus clock maximum frequency	100	100	100	MHz
F_ADMAMAX	LPD-DMA maximum frequency	600	500	500	MHz
F_{APLL_TO_LPDMAX}	APLL_TO_LPD maximum frequency	533	533	533	MHz
F_{DPLL_TO_LPDMAX}	DPLL_TO_LPD maximum frequency	533	533	533	MHz
F_{VPLL_TO_LPDMAX}	VPLL_TO_LPD maximum frequency	533	533	533	MHz
F_{IOPLL_TO_FPDMAX}	IOPLL_TO_FPD maximum frequency	533	533	533	MHz
F_{RPLL_TO_FPDMAX}	RPLL_TO_FPD maximum frequency	533	533	533	MHz