PS Clocks - DS925

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2025-09-26
Revision
1.29 English
Table 1. PS Reference Clock Requirements
Symbol Description 1 Min Typ Max Units
TRMSJPSCLK PS_REF_CLK input RMS clock jitter – – 3 ps
TPJPSCLK

PS_REF_CLK input period jitter (peak-to-peak)

Number of clock cycles = 10,000

 – – 50 ps
TDCPSCLK PS_REF_CLK duty cycle 45 – 55 %
TRFPSCLK PS_REF_CLK rise time (20%–80%) and fall time (80%–20%) – – 2.22 ns
FPSCLK PS_REF_CLK frequency 27 – 60 MHz
  1. The values in this table are applicable to alternative PS reference clock inputs ALT_REF_CLK, AUX_REF_CLK, and VIDEO_CLK.
Table 2. PS RTC Crystal Requirements
Symbol Description 1 Min Typ Max Units
FXTAL Parallel resonance crystal frequency – 32.8 – KHz
TFTXTAL Frequency tolerance –20 – 20 ppm
CXTAL Load capacitance for crystal parallel resonance – 12.5 – pF
RESR Crystal ESR (16.8 and 19.2 MHz) – 70 – KΩ
CSHUNT Crystal shunt capacitance – 1.4 – pF
  1. See the crystal circuit example in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
Table 3. PS PLL Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
TLOCKPSPLL PLL maximum lock time 100 100 100 µs
FPSPLLMAX PLL maximum output frequency 1600 1600 1600 MHz
FPSPLLMIN PLL minimum output frequency 750 750 750 MHz
FPSPLLVCOMAX PLL maximum VCO frequency 3000 3000 3000 MHz
FPSPLLVCOMIN PLL minimum VCO frequency 1500 1500 1500 MHz
Table 4. PS Reset Assertion Timing Requirements
Symbol Description Min Typ Max Units
TPSPOR Required PS_POR_B assertion time 1 10 – – µs
TPSRST Required PS_SRST_B assertion time 3 – – PS_REF_CLK Clock Cycles
  1. PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of TPSPOR after all the PS supply voltages reach minimum levels. PS_POR_B must be asserted Low for the duration of TPOR,MAX when the PS and PL power-up at the same time and the application uses both the PS and PL after power-up.
Table 5. PS Clocks Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
FTOPSW_MAINMAX FPD AXI interconnect clock maximum frequency 600 533 533 MHz
FTOPSW_LSBUSMAX FPD APB bus clock maximum frequency 100 100 100 MHz
FGDMAMAX FPD-DMA controller clock maximum frequency 600 600 600 MHz
FDPDMAMAX DisplayPort controller clock maximum frequency 600 600 600 MHz
FLPD_SWITCH_CTRLMAX LPD AXI interconnect clock maximum frequency 600 500 500 MHz
FLPD_LSBUS_CTRLMAX LPD APB bus clock maximum frequency 100 100 100 MHz
FADMAMAX LPD-DMA maximum frequency 600 500 500 MHz
FAPLL_TO_LPDMAX APLL_TO_LPD maximum frequency 533 533 533 MHz
FDPLL_TO_LPDMAX DPLL_TO_LPD maximum frequency 533 533 533 MHz
FVPLL_TO_LPDMAX VPLL_TO_LPD maximum frequency 533 533 533 MHz
FIOPLL_TO_FPDMAX IOPLL_TO_FPD maximum frequency 533 533 533 MHz
FRPLL_TO_FPDMAX RPLL_TO_FPD maximum frequency 533 533 533 MHz