Virtex Line Buffer - 2020.2 English

Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958)

Document ID
UG958
Release Date
2020-11-18
Version
2020.2 English

The Xilinx Virtex Line Buffer reference block delays a sequential stream of pixels by the specified buffer depth.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Parameters specific to this reference block are as follows:

  • Buffer Depth: Number of samples the stream of pixels is delayed.
  • Sample Period: Sample rate at which the block will run