n-tap Dual Port Memory MAC FIR Filter - 2020.2 English

Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958)

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2020.2 English

The Xilinx n-tap Dual Port Block RAM MAC FIR Filter reference block implements a multiply-accumulate-based FIR filter. One dedicated multiplier and one dual port block RAM are used in the filter. The filter configuration illustrates a technique for storing coefficients and data samples in filter design. The Virtex FPGA family (and Virtex family derivatives) provide dedicated circuitry for building fast, compact adders, multipliers, and flexible memory architectures. The filter design takes advantage of these silicon features by implementing a design that is compact and resource efficient.

Implementation details are provided in the filter design Subsystems. To read the annotations, place the block in a model, then right-click on the block and select Explore from the popup menu. Double click on one of the sub-blocks to open the sub-block model and read the annotations.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Parameters specific to this reference block are as follows:

  • Data Input Bit Width: Width of input sample.
  • Data Input Binary Point: Binary point location of input.
  • Coefficients: Specify coefficients for the filter. Number of taps is inferred from size of coefficient vector.
  • Number of Bits per Coefficient: Bit width of each coefficient.
  • Binary Point per Coefficient: Binary point location for each coefficient.
  • Sample Period: Sample period of input.


  • J. Hwang and J. Ballagh. Building Custom FIR Filters Using System Generator. 12th International Field-Programmable Logic and Applications Conference (FPL). Montpellier, France, September 2002. Lecture Notes in Computer Science 2438