Revision History - 2020.2 English

Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958)

Document ID
UG958
Release Date
2020-11-18
Version
2020.2 English
The following table shows the revision history for this document.
Section Revision Summary
11/18/2020 Version 2020.2
Xilinx Blockset
Xilinx SSR Blockset Clarification to Vector DDFS.
System Generator Utilities Clarification to xlTBUtils.
06/03/2020 Version 2020.1
Xilinx Blockset Clarifications to the following blocks:
  • Single-Port RAM
  • ROM
  • Dual-Port RAM
  • AXI FIFO
Throughout document Editorial updates.