4-channel 8-tap Transpose FIR Filter - 2020.2 English

Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958)

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2020.2 English

The Xilinx 4-channel 8-tap Transpose FIR Filter reference block implements a 4-channel 8-tap transpose FIR filter. The transpose structure is well suited for data path processing in Xilinx FPGAs, and is easily extended to produce larger filters (space accommodating). The filter takes advantage of silicon features found in the Virtex family FPGAs such as dedicated circuitry for building fast, compact adders, multipliers, and flexible memory architectures.

Implementation details are provided in the filter design Subsystems. To read the annotations, place the block in a model, then right-click on the block and select Explore from the popup menu. Double click on one of the sub-blocks to open the sub-block model and read the annotations.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Parameters specific to this reference block are as follows:

  • Coefficients: Specify coefficients for the filter. Number of taps is inferred from size of coefficient vector.
  • Number of Bits per Coefficient: Bit width of each coefficient.
  • Binary Point for Coefficient: Binary point location for each coefficient.
  • Number of Bits per Input Sample: Width of input sample.
  • Binary Point for Input Samples: Binary point location of input.
  • Input Sample Period: Sample period of input.