m-channel n-tap Transpose FIR Filter - 2020.2 English

Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958)

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2020.2 English

The Xilinx m-channel n-tap Transpose FIR Filter uses a fully parallel architecture with Time Division Multiplexing. The Virtex FPGA family (and Virtex family derivatives) provide dedicated shift register circuitry called the SRL16E, which are exploited in the architecture to achieve optimal implementation of the multichannel architecture. The Time Division Multiplexer and Time Division Demux can be selected to be implemented or not. Embedded Multipliers are used for the multipliers.

As the number of coefficients changes so to does the structure underneath as it is a dynamically built model.

Implementation details are provided in the filter design Subsystems. To read the annotations, place the block in a model, then right-click on the block and select Explore from the popup menu. Double click on one of the sub-blocks to open the sub-block model and read the annotations.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Parameters specific to this reference block are as follows:

  • Input Bit Width: Width of input sample.
  • Input Binary Point: Binary point location of input.
  • Coefficients: Specify coefficients for the filter. Number of taps is inferred from size of coefficient vector.
  • Coefficients Bit Width: Bit width of each coefficient.
  • Coefficients Binary Point: Binary point location for each coefficient.
  • Number of Channels: Specify the number of channels desired. There is no limit to the number of channels supported.
  • Time Division Multiplexer Front End: The TDM front-end circuit can be implemented or not (if the incoming data is already TDM)
  • Time Division DeMultiplexer Back End: The TDD back-end circuit can be implemented or not (if you desire a TDM output). This is useful if the filter feeds another multichannel structure.
  • Input Sample Period: Sample period of input.