WRITE Command - 1.0 English

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID

PG381

Release Date

2023-10-18

Version

1.0 English

Table 1. WRITE CSV Command Format for AXI3/AXI4
Command Input Field	Width	Non-Synthesizable TG Options
txn_count	32/STRING	<value in decimal> Transaction count. Repeat the current command <N> times, where N = value. <value in decimal>KB Amount of data to be transferred in KB, for example 50 KB, 100 KB. <value in decimal>MB Amount of data to be transferred in MB, for example 5 MB, 10 MB. <value in decimal>GB Amount of data to be transferred in GB, for example 1 GB, 2 GB. INF Repeat the current command infinitely.
start_delay	32/STRING	<value in decimal> Value in number of clocks. Issue transaction after specified number of clocks <value in decimal>MBps Bandwidth value for Write transactions, for example 12500 MB/s. Note: 1 MB/s = 1,000,000 Bps (Bytes per second).
inter_beat_delay	32	<value in decimal> Value in number of clocks. Adds specified number of clocks between two Write data beats in a transaction
wdata_pattern	STRING	constant random walking_0 walking_1 hammer same_as_src same_as_addr same_as_addr_xor same_as_id same_as_burst same_as_len same_as_size same_as_cache Note: Data pattern details are described in the Data Patterns section.
wdata_pat_value	512	<value in hex> When the wdata_pattern field is set to constant, this field value is used as constant data which is sent on all Write data beats (wdata_pattern: constant). <seed_value in hex> When wdata_pattern field is selected as “random”, this field value is used as seed for RNG (wdata_pattern: random).
data_integrity	STRING	enabled Data integrity checks will be enabled for the Write transaction. The Write transaction details are stored in the AXI TG sparse memory to do comparison later when a Read occurs to this location. disabled Data integrity checks will be disabled for the Write transaction, and details arel not stored in the AXI TG sparse memory.
dest_id	12	<value in hex> The targeted NoC slave destination ID value (12-bit value) can be given in this field for the transaction. The dest_id value is sent on the nmu_wr_usr_dst signal along with AXI Write requests.
base_addr	64	<value in hex> The base_addr can be specified in this field. The incremented address for the transactions is looped back to the base address when the high address boundary is reached. In case of randomized address, the TG generates the address between base_addr and high_addr.
high_addr	64	<value in hex> The high address can be specified here. Up to this value the address is incremented by the TG. When the incremented address reaches the high address boundary, the next transaction start address is the base_addr. In case of a randomized address, TG generates the address between base_addr and high_addr.
addr_incr_by	64/STRING	<value in hex> This field value is considered as “value in hex” when the axi_addr_offset field is set to a start address offset value. The first transaction start address (SA) will be picked from the axi_addr_offset and base_addr fields (SA = base_addr + axi_addr_offset). From the second transaction onwards for each AXI transaction, the start address is incremented by the specified addr_incr_by value. For example: txn_count=4, base_addr=0x0_0000, high_addr=0xF_FFFFF, addr_incr_by=0x41, axi_addr_offset=0x01, axi_len=0, axi_size=4. 1st transaction: AWADDR=0x0_0001 2nd transaction: AWADDR=0x0_0042 3rd transaction: AWADDR=0x0_0083 4th transaction: AWADDR=0x0_00C4 <seed_value in hex> This field value is considered as seed for RNG to generate random addresses when the axi_addr_offset field is set to random address options. auto_incr The first transaction start address (SA) is picked from the axi_addr_offset and base_addr fields (SA = base_addr + axi_addr_offset). From second transaction onwards for each AXI transaction issued, the start address is calculated using the expression described below.
addr_incr_by (continued)	64/STRING	INCR/WRAP Burst auto_incr The first transaction start address (SA) will be picked from the axi_addr_offset and base_addr fields (SA = base_addr + axi_addr_offset). From second transaction onwards for each AXI transaction issued, the start address is calculated using the following expression: start_address (from second transaction onwards) = previous_start_address + ((2^axi_size) * (axi_len+1)) For example: txn_count= 3, base_addr= 0x0000_0000, high_addr= 0xFFFF_FFFF, axi_addr_offset= 0x0000_0000, axi_size= 6, axi_len= 0, axi_burst= 1(INCR). The start addresses of all three transactions are as follows: 1st transaction start address: 0x0000_0000 2nd transaction start address: 0x0000_0000 + ((2^6)(0+1)) = 0x0000_0040 3rd transaction start address: 0x0000_0040 + ((2^6)(0+1)) = 0x0000_0080
addr_incr_by (continued)	64/STRING	FIXED Burst auto_incr The first transaction start address (SA) is picked from the axi_addr_offset and base_addr fields (SA = base_addr + axi_addr_offset). From second transaction onwards for each AXI transaction issued, the start address is calculated using the following expression: start_address (from second transaction onwards) = previous_start_address + (2^axi_size) For example, txn_count= 3, base_addr= 0x0000_0000, high_addr= 0xFFFF_FFFF, axi_addr_offset= 0x0000_0000, axi_size= 5, axi_len= 4, axi_burst= 0(FIXED). The start addresses of all three transactions are as follows: 1st transaction start address: 0x0000_0000 2nd transaction start address: 0x0000_0000 + (2^5) = 0x0000_0020 3rd transaction start address: 0x0000_0020 + (2^5) = 0x0000_0040
axi_addr_offset	64/STRING	<value in hex> This is the offset value added to base_addr to calculate the start address of the first transaction. From the second transaction onwards, the start address is calculated based on the addr_incr_by field option. If the next transaction address reaches the high_addr boundary it is looped back to base_addr. random Any random address is generated between base_addr and high_addr. The addr_incr_by field value is set as seed to RNG. random_aligned Any random aligned address is generated between base_addr and high_addr. addr_incr_by field value is set as seed to RNG. random_unaligned Any random unaligned address is generated between base_addr and high_addr.The addr_incr_by field value is set as seed to RNG. Note: To generate an address that is aligned to the transaction size (that is, (len+1) * 2^size), use the SET_DEFAULT command addr_mask option to set the required LSB address bits to 0.
axi_len	8/STRING	<value in hex> Write transactions is sent with the specified AXI length value. Width: 4 for AXI3, 8 for AXI4. all Generates all length values in transactions. The first transaction is sent with an axi_len of 0x0 and then incremented on each consecutive AXI transaction. When MAX_LEN is reached, the transaction starts again from an axi_len of 0x0 and increments until MAX_LEN is reached, and so on. Note: For AXI3, MAX_LEN = 0xF. For AXI4, MAX_LEN varies depending on AWSIZE due to the 4k Boundary limit: When AWSIZE is 64B, MAX_LEN is 0x3F. When AWSIZE is 32B, MAX_LEN is 0x7F. When AWSIZE is 16, 8, 4, 2 or 1B, MAX_LEN is 0xFF.
axi_size	3/STRING	<value in hex> Write transactions is sent with the specified AXI size value. all Generates all the size values in transactions. The first AXI transaction is sent with MAX_SIZE and the size is decremented with each consecutive transaction. When it reaches 0x0, transactions start again from MAX_SIZE and decrements until 0x0 is reached again and so on. Note: MAX_SIZE = $clog2(AXI Data Width/8).
axi_id	16/STRING	<value in hex> Write transactions are sent with the specified AXI ID value. auto_incr The first Write transaction is sent out with an ID of 0x0 and each consecutive transaction ID is incremented by 0x1. When the ID reaches MAX_ID value, it starst again from 0x0 and increments until MAX_ID is reached again, and so on. Note: MAX_ID = 2^AXI ID Width - 1
axi_burst	2/STRING	<value in hex> Supported values are 0x0, 0x1, 0x2. <value in string> Supported values are FIXED, INCR, WRAP.
axi_lock	2/STRING	<value in hex> Supported values are 0x0, 0x1. <value in string> Supported values are NORMAL, EXCLUSIVE.
axi_cache	4/STRING	<value in hex> <value in string> Supported values are MOD, NON_MOD. Note: In the <value in string> option, MOD denotes that the AXI Write transaction is modifiable (AWCACHE = 0x2) by the slave/interconnect. NON_MOD denotes that the AXI Write transaction is non-modifiable (AWCACHE = 0x0) by the slave/interconnect.
axi_prot	3	<value in hex>
axi_qos	4	<value in hex>
axi_region	4	<value in hex>
axi_user (for AWUSER)	16	<value in hex>
exp_resp	STRING	OKAY AXI Write responses should come as expected as OKAY, otherwise the TG will error out. EXOKAY AXI Write responses should come as expected as EXOKAY, otherwise the TG will error out. SLVERR AXI Write responses should come as expected as SLVERR, otherwise the TG will error out. DECERR AXI Write responses should come as expected as DECERR, otherwise the TG will error out. <Blank/Empty_Field> Leaving the exp_resp field Empty/Blank/Unfilled. In this case, TG does not do any expected response check. Instead, it treats the AXI responses in a standard manner; that is, if any responses are coming as SLVERR or DECERR, the TG will error out.