AXI4-Lite Interface - 1.0 English

The AXI4-Lite interface provides read/write access to the configuration and status registers in the Traffic Generator and also allows you to load the block RAM with instructions. All the transactions through the AXI4-Lite interface are of 32-bit data width. If you are loading an instruction into the block RAM with a width exceeding 32-bit, you must send multiple AXI4-Lite transactions, each of them 32-bit wide with the address bus value bits [5:2] incrementing each transaction starting from 4’b0000 up to 4’b1111, keeping all the other address bits constant till the complete instruction is loaded into a single memory location in the block RAM. See Running Custom Traffic for the Synthesizable TG for a programming example.

For example, if you consider the width of block RAM memory inside the TG as 416-bit and you want to load an instruction at block RAM address location 0x004 for Traffic Generator 2, the address format looks like the following table, with bits [5:2] incrementing for 4’b0000 – 4’b1011. In total 13 transactions are required to load a 416-bit wide instruction into a single block RAM location.

See User Guidelines for information on Data Integrity.