| Signal | I/O | Port Width | Description |
|---|---|---|---|
| Default Signals | |||
clk
|
I | 1 | Traffic Generator clock (AXI clock) |
pclk
|
I | 1 | Clock for instruction block RAM loading |
tg_rst_n
|
I | 1 | Traffic Generator reset |
axi_tg_start
|
I | 1 | Start signal indicating to start the traffic from TG |
axi_tg_done
|
O | 1 | All instructions executed status |
axi_tg_error
|
O | 1 | TG error status |
trigger_in
|
I | 1 | Input trigger for synchronization |
trigger_out
|
O | 1 | Output trigger for synchronization |
nmu_wr_usr_dst
|
O | 12 | Write destination ID |
nmu_rd_usr_dst
|
O | 12 | Read destination ID |
| VIO Interface Signals | |||
vio_aclk
|
I | 1 | VIO clock |
vio_aresetn
|
I | 1 | VIO reset |
s_axis_vio_tdata
|
I | 32 | The primary payload that is used to provide the data |
s_axis_vio_tlast
|
I | 1 | Indicates the boundary of a packet |
s_axis_vio_tready
|
O | 1 | Indicates that the slave can accept a transfer |
s_axis_vio_tvalid
|
I | 1 | Indicates that the master is driving a valid transfer |
| MCS Interface Signals | |||
s_addr_strobe
|
I | 1 | Address strobe for address |
s_address
|
I | 30 | Address |
s_read_data
|
O | 32 | Read data |
s_read_strobe
|
I | 1 | Read strobe for read data |
s_ready
|
O | 1 | Ready signal |
s_write_data
|
I | 32 | Write data |
s_write_strobe |
I | 1 | Write strobe for Write data |
| AXI Signals | |||
|
|
I/O | Varies based on configuration | AXI3/AXI4 master interface signals. See AMBA AXI protocol specification for AXI3, AXI4 |
| AXI4-Stream Signals | |||
axis_t*
|
I/O | Varies based on configuration | AXI4-Stream master interface signals. See AMBA AXI protocol specification for AXI4-Stream. |