The TG architecture for AXI4-Stream operation is shown in the following figure.
The TG is designed to support high bandwidth unidirectional data transfers. An
instruction block RAM is present in the instruction core module of the TG with a depth
of 512. This means up to 512 CSV instructions can be loaded in the block RAM and each
CSV instruction can have up to 65,536 stream Write requests or a single Wait request.
The Instruction Core module reads the block RAM instructions one by one, decodes them
and provides the information to the Stream Channel Control module that pumps up the
AXI4-Stream traffic. The AXI4-Stream Channel Control module receives control information from the
Instruction Core module and generates stream traffic with multiple data pattern options.
The packet length is programmable to up to 65,536 beats per request. Additionally,
TLAST can be configured to be always one or always
zero. The TG also supports infinite transaction and infinite loop counts, that allow the
traffic generator to run indefinitely.