| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 31:0 | 0x0000_0000 | RO |
Write bandwidth counter. Number of cycles from the start of the TG to the wrch_done signal, a Write Traffic Done signal mapped to Bit 8 of the FLOW_EMPTY register. This is used to calculate the bandwidth. Write bandwidth = WRBEAT_CNTR/ WBW_EFF_CLK_CNTR This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset. |