|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive
SoC |
| Supported User Interfaces |
AXI3
3
, AXI4, and AXI4-Stream
|
| Provided with
Core
|
| Design Files |
RTL |
| Example Design |
Not Provided |
| Test Bench |
Not Provided |
| Constraints File |
XDC |
| Simulation Model |
N/A |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75781
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs:
72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
-
AXI3 is
only supported for the Non-Synthesizable TG. It is not supported for the
Synthesizable TG.
|