In this mode, the instructions can be loaded into the instruction block RAM using either the VIO interface from the Simulation Trigger for the NoC AXI TG IP core, or the AXI4-Lite interface. The addressing of the block RAM is specified in Block RAM Addressing: 0x8000 to 0xFFFC. In this mode configure the TG_START Register (0x4004) to manually start the traffic generators. The status can be monitored through the same VIO or AXI4-Lite interface.