Data patterns for AXI4 - 1.0 English

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID
PG381
Release Date
2023-10-18
Version
1.0 English

The following data patterns are supported by the Synthesizable TG for AXI4.

Table 1. Data Patterns for the Synthesizable TG for AXI4
Data Format Options
Constant
  • The user-defined data byte is constantly sent on all bytes of the Write data beat.
  • You can set the data byte value in the wdata_pat_value CSV field.
  • For example, if wdata_pat_value = 0x032, AXI Data Width = 64, and axi_size = 3, all the data_beat values of the given instruction is sent as 0x3232_3232_3232_3232.
SAME_AS_ADDR
  • The corresponding AXI beat byte address (LSB 8 bits) is sent as data in the bytes of the Write beat.
  • You can select the same_as_addr data pattern by setting the wdata_pat_value CSV field to 0x100.
  • For example, if wdata_pat_value = 0x100, AXI Data Width = 64, axi_addr = 0x0200_0000_11A0, axi_burst = INCR, axi_len = 3, and axi_size = 3, data beats are generated as follows:
    • Byte_Lane0 address on Beat0= 0x0200_0000_11A0 --> LSB 8 bits are A0 which are sent as Write data on byte_lane0 of beat0.
    • Byte_Lane1 address on Beat0= 0x0200_0000_11A1 --> LSB 8 bits are A1 which are sent as Write data on byte_lane1 of beat0.
    • Beat0 = 0xA7A6_A5A4_A3A2_A1A0
    • Beat1 = 0xAFAE_ADAC_ABAA_A9A8
    • Beat2 = 0xB7B6_B5B4_B3B2_B1B0
    • Beat3 = 0xBFBE_BDBC_BBBA_B9B8
SAME_AS_ADDR_XOR
  • The corresponding AXI beat byte address is bytewise folded, XORed, and sent as data in the bytes of the Write beat.
  • You can select the same_as_addr_xor data pattern by setting the wdata_pat_value CSV field to 0x101.
  • For example, if wdata_pat_value = 0x101, AXI Data Width = 64, axi_addr = 0x0200_0000_11A0, axi_burst = INCR, axi_len = 3, and axi_size = 3, data beats are generated as follows:
    • Byte_Lane0 address on Beat0= 0x0200_0000_11A0 --> 0x02^0x00^0x00^0x00^0x11^0xA0= 0x B3. It is sent as Write data on byte_lane0 of beat0.
    • Byte_Lane1 address on Beat0= 0x0200_0000_11A1 --> 0x02^0x00^0x00^0x00^0x11^0xA1= 0x B2. It is sent as Write data on byte_lane1 of beat0.
    • Beat0 = 0xB4B5_B6B7_B0B1_B2B3
    • Beat1 = 0xBCBD_BEBF_B8B9_BABB
    • Beat2 = 0xA4A5_A6A7_A0A1_A2A3
    • Beat3 = 0xACAD_AEAF_A8A9_AAAB
Hammer
Note: Hammer data is only supported on full transfer AXI transactions for the Synthesizable TG. Selecting hammer data on a narrow transfer might result in unpredictable behavior.
  • Hammer data has a long number of tail bits (MSBs) with value 0 or 1 and a short number of header bits (LSBs) with an inverted bit value in a data beat. The values of the tail bits (width of ¾ of axi_size_in_bits) and header bits (width of ¼ of axi_size_in_bits) are generated based on the corresponding AXI beat address. If the resulting value of beat_start_address divided by axi_size_in_bytes is even the header bits are 1 and the tail bits are 0. If the resulting value is odd the header bits are 0 and tail bits are 1.
  • You can select the hammer data pattern by setting the wdata_pat_value CSV field to 0x102.
For example, if wdata_pat_value = 0x102, AXI Data Width = 64, axi_addr = 0x0000_0000_11A5, axi_burst = INCR, axi_len = 3, and axi_size = 3, data beats are generated as follows:
  • header_width = axi_size_in_bits/4 = 64/4 = 16
  • tail_width = (axi_size_in_bits*3)/4 = (64*3)/4 = 48
  • Beat0 calculation:

    Aligned(beat_start_address)/axi_size_in_bytes = 0x0000_0000_11A0/8 = 0x234(even value)

    So, header bits are 16{{1’b1}} and tail bits are 48{{1’b0}}.

    Beat0 = 0x0000_0000_0000_FFFF

  • Beat1 calculation:

    Aligned(beat_start_address)/axi_size_in_bytes = 0x0000_0000_11A8/8 = 0x235(odd value)

    So, header bits are 16{{1’b0}} and tail bits are 48{{1’b1}}.

    Beat1 = 0xFFFF_FFFF_FFFF_0000

  • Beat2 calculation:

    Aligned(beat_start_address)/axi_size_in_bytes = 0x0000_0000_11B0/8 = 0x236(even value)

    So, header bits are 16{{1’b1}} and tail bits are 48{{1’b0}}.

    Beat2 = 0x0000_0000_0000_FFFF

  • Beat3 calculation:

    Aligned(beat_start_address)/axi_size_in_bytes = 0x0000_0000_11B8/8 = 0x237(odd value)

    So, header bits are 16{{1’b0}} and tail bits are 48{{1’b1}}.

    Beat3 = 0xFFFF_FFFF_FFFF_0000