Port Description - 1.0 English

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID: PG381
Release Date: 2023-10-18
Version: 1.0 English

Table 1. Non-Synthesizable TG
Signal	I/O	Port Width	Description
`clk`	I	1	Traffic Generator clock (AXI clock)
`tg_rst_n`	I	1	Traffic Generator reset
TG Control Signals
`axi_tg_start`	I	1	The execution of AXI-TG starts when this signal is asserted. If no synchronization with `init_calib_complete` or other TGs is required, tie this signal to `tg_rst_n`.
`axi_tg_done`	O	1	When asserted, it indicates that all Write/Read transactions are completed
`axi_tg_error`	O	1	When asserted, indicates that the TG is encountered an error condition
`trigger_in`	I	1	Input trigger for synchronization
`trigger_out`	O	1	Output trigger for synchronization
AXI Signals
`axi_aw` `axi_w` `axi_b` `axi_ar` `axi_r*`	I/O	Varies based on configuration	AXI3/AXI4 master interface signals. See AMBA AXI protocol specification for AXI3, AXI4.
AXI4-Stream Signals
axis_t*	I/O	Varies based on configuration	AXI4-Stream master interface signals. See AMBA AXI protocol specification for AXI4-Stream.
NoC IP Specific Signals
`nmu_wr_usr_dst`	O	12	Sends the destination slave ID for Write/Stream transactions. Only used when the TG is connected to AMD Versal™ NoC NMU (NoC Master Unit).
`nmu_rd_usr_dst`	O	12	Sends the destination slave ID for Read transactions. Only used when the TG is connected to Versal NoC NMU (NoC Master Unit).