Register Space - 1.0 English

The Performance AXI Traffic Generator has a set of registers to control its behavior, to provide status and debug information, and to control external signals.

These registers are classified into control/configuration registers and status registers. The control registers hold the control information required by the TG. This information is written through the register I/O interface (MCSIO_IN) on a slow clock (PCLK). The status registers hold the status information generated by the TG on a faster clock (ACLK) and this information can be read through the register I/O interface. The asynchronous clock domain crossing circuit ensures data integrity between the register space and the TG core. The TG registers can be accessed through the TG register interface (MCSIO_IN). By default this interface is hidden in the TG. Enable the Traffic Reloading option in the TG to gain access to the register interface.

The dedicated Simulation Trigger for the NoC AXI TG is a companion IP to the Performance AXI Traffic Generator and can be used to extend the register I/O interface to a typical user I/O interface such as VIO or AXI4-Lite. The Simulation Trigger IP converts the VIO/AXI4-Lite traffic into register interface traffic. The user I/O can be selected on the Traffic Reloading section of this IP. When you select one of the above options, the MCSIO_OUT register access interface appears in the Simulation Trigger IP. Connect it to the MCSIO_IN interface of the TG to send/receive register transactions.

A register space block diagram along with the interfaces to other blocks is shown in the following figure:

Figure 1. Register Space Block Diagram