AXI_VLD_RDY_STATS Register (0x21B0) - AXI_VLD_RDY_STATS Register (0x21B0) - 1.0 English - PG381

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)
Document ID
PG381
Release Date
2023-10-18
Version
1.0 English
Table 1. AXI_VLD_RDY_STATS Register (0x21B0)
Bit Default Value Access Type Description
31:10 0 RO Reserved
9 0 RO Current status of awvalid signal.

This register is used in case of hang, to check the master status.
8 0 RO Current status of awready signal.

This register is used in case of hang, to check the slave status.
7 0 RO Current status of wvalid signal.

This register is used in case of hang, to check the master status.
6 0 RO Current status of wready signal.

This register is used in case of hang, to check the slave status.
5 0 RO Current status of bvalid signal.

This register is used in case of hang, to check the slave status.
4 0 RO Current status of bready signal.

This register is used in case of hang, to check the master status.
3 0 RO Current status of arvalid signal.

This register is used in case of hang, to check the master status.
2 0 RO Current status of arready signal.

This register is used in case of hang, to check the slave status.
1 0 RO Current status of rvalid signal.

This register is used in case of hang, to check the slave status.
0 0 RO Current status of rready signal.

This register is used in case of hang, to check the master status.