| Field Name | Bit Fields | Width | Description |
|---|---|---|---|
|
axiUser/ phase_done |
[3:0] | 4 |
AXI user field for Read/Write commands. For phase done command, bit 0 must be set to 1. |
| axiRegion | [7:4] | 4 | AXI Region field |
| axiQos | [11:8] | 4 | AXI Qos field |
| axiProt | [14:12] | 3 | AXI Prot field |
| axiCache | [18:15] | 4 | AXI Cache field |
| axiLock | [20:19] | 2 | AXI Lock field |
| axiBurst | [22:21] | 2 | AXI Burst field |
| axiSize | [25:23] | 3 | AXI Size field |
| axiLen | [33:26] | 8 | AXI Length field |
| ID Type | [34] | 1 |
1'b0: constant awid/arid 1'b1: incremental awid/arid |
| Number of Transactions | [50:35] | 16 | Number of transactions per command |
| Transaction Type | [52:51] | 2 |
2'b00: READ command 2'b01: WRITE command 2'b10: WAIT command |
| Number of bytes per transaction | [100:53] | 48 | If the address pattern field is 2'b00, "Linear address", then this field is equal to (2 ^ axiSize)*(axiLen + 1) for WRAP and INCR bursts and equal to (2 ^ axiSize) for FIXED burst. If the address pattern field is 2'b01, "increment by value", then this field is equal to a constant value by which the transaction address is incremented. [JBK15] |
| Address offset | [148:101] | 48 | This is the offset value that are added to the base address to calculate the address of the first transaction of a command. If the next transaction reaches the boundary of the high address then the base address is loaded. |
| High Address | [196:149] | 48 | Up to this value the address will be incremented by the TG. When the incremented address reaches the high address boundary, the next transaction start address will be the base address. |
| Base Address | [244:197] | 48 | The base address can be specified in this field. The incremented address for the transaction will be looped back to the base address when the high address boundary is reached. |
| Seed | [292:245] | 48 | This field specifies the seed value for random address generation. |
| Address pattern | [294:293] | 2 |
2'b00: Linear address. The next transaction address will be incremented by the number of bytes accessed in the current transaction. 2'b01: Increment by value. The next transaction address will be incremented by this value. 2'b10: Random address. Seed field is used to generate the random addresses using a PRBS pattern generator. 2'b11: Random aligned address. The random address generated by the PRBS module will be aligned. |
| Loop Address | [303:295] | 9 | When loop is used in the CSV field, this field indicates to which instruction to loop back. |
| Loop | [304] | 1 | When loop is used in the CSV field, set this bit High for the last instructions in the loop. |
| Last Instruction | [305] | 1 | This bit indicates the last instruction. |
| Infinite Transaction | [306] | 1 | If the bit is set, then the instruction is executed forever. |
| Delay between Transactions | [322:307] | 16 | Specifies the delay between each transaction in clock cycles |
| Loop count | [338:323 | 16 | When loop is used in the CSV field, this field indicates how many times to loop the instructions. |
| Infinite Loop | [339] | 1 | When loop is used in the CSV field, this field indicates loop the instruction forever. |
| Loop Start | [340] | 1 | Not used |
| Destination ID | [352:341] | 12 | This value is set on the destination ID output signal. |
| DI Enable | [353] | 1 | If set, enables the data integrity of corresponding read instructions. |
| Data Patterns | [362:354] | 9 |
If the MSB is 0, the next eight bits will be sent as data. Otherwise, the three LSBs will specify the data pattern. 9'b1_0000_0000: Address as data (same_as_addr) 9'b1_0000_0001: Byte XOR of address as data (same_as_addr_xor) 9'b1_0000_0010: Hammer data 9'b1_0000_0011: Reserved 9'b1_0000_0100: Reserved 9'b1_0000_0101: Reserved 9'b1_0000_0110: Reserved 9'b1_0000_0111: Reserved |
| Loop Increment value | [378:363] | 16 | This value specifies the address to be incremented for each loop count |
| ID value | [394:379] | 16 | AXI ID value |
| Expected response | [397:395] | 3 |
Expected response for RRESP and BRESP MSB bit indicates expected response field is valid. 3’b100: OKAY 3’b101: EXOKAY 3’b110: SLVERR 3’b111: DECERR 3’b0xx: check has to be done based on axi_lock signal |
| User 10 bit | [407:398] | 10 | User data of 10 bits |
| Last write/Read | [409:408] | 2 | Indicates last Read or Write instruction |
| User 11th bit | 410 | 1 | 11th bit of user data |