Important:
AXI3 is only supported in the Non-Synthesizable TG. It is not supported
for the Synthesizable TG when running simulations or in hardware.
- Supports aligned or unaligned and full or narrow transfers
- Supports random address, auto increment address, and increment address by a specific value
- Supports configurable data patterns
- Supports control of start address and high address
- Supports Incremental, Wrap, and Fixed bursts
- Supports exclusive transactions
- Supports data integrity checking
- Optional performance counters to measure bandwidth and latency numbers for the synthesizable TG