Figure 1. Synthesizable TG Options Tab
- Path to User Defined Pattern File (CSV) for Synthesizable TG
- The location of the CSV file must be added here.
- Data Integrity
-
Disabled
Enabled with Constant ID
Enabled with Incremental ID
- Number of Data Integrity errors to stop Traffic
- Values supported are 0 to 256 in which 0 means never stop traffic.
- Latency Calculation
-
Disabled
Enabled with Constant ID
Enabled with Incremental ID
- AXI Address Width
- 48 bits
- AXI ID Width
-
Up to 16 when Data Integrity is disabled
Up to 4 with Incremental ID
1 for Constant ID
- Traffic Reloading
- Enables the register I/O interface to access the TG register space and BRAM instruction loading. Enabling this feature requires a Simulation Trigger IP in your design.
- Insert VIO for Debug Status Signal
- Enables VIO debug monitoring for status signals. The following signals are
available on VIO .
- tg_done: When asserted, it indicates that all Write/Read transactions are completed.
- tg_error: When asserted, it indicates that the TG has encountered an error condition like a Data integrity error.
- wrch_done: When asserted, it indicates that all Write transactions are completed.
- rdch_done: When asserted, it indicates that all Read transactions are completed.
- Insert ILA for Debug Status Signals
- Enables an ILA core for live monitoring of traffic status.
Following AXI signals are available on the ILA .
- AWREADY
- AWVALID
- AREADY
- ARVALID
- WREADY
- WVALID
- WLAST
- BREADY
- BVALID
- BRESP
- RREADY
- RVALID
- RLAST
- RRESP